>-----Original Message----- >From: Ville Syrjälä [mailto:ville.syrjala@xxxxxxxxxxxxxxx] >Sent: Wednesday, October 31, 2018 2:08 PM >To: Srivatsa, Anusha <anusha.srivatsa@xxxxxxxxx> >Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Singh, Gaurav K <gaurav.k.singh@xxxxxxxxx>; >Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>; Navare, Manasi D ><manasi.d.navare@xxxxxxxxx> >Subject: Re: [v4 6/7] i915/dp/fec: Configure the Forward Error Correction bits. > >On Tue, Oct 30, 2018 at 05:45:16PM -0700, Anusha Srivatsa wrote: >> If FEC is supported, the corresponding DP_TP_CTL register bits have to >> be configured. >> >> The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register and >> wait till FEC_STATUS in DP_TP_CTL[28] is 1. >> Also add the warn message to make sure that the control register is >> already active while enabling FEC. >> >> v2: >> - Change commit message. Configure fec state after >> link training (Manasi, Gaurav) >> - Remove redundent checks (Manasi) >> - Remove the registers that get added automagically (Anusha) >> >> v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav) >> >> v4: rebased. >> >> v5: >> - Move the code to the proper spot, according to spec.(Ville) >> - Use fec state as a check too. >> >> Cc: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx> >> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> >> Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> >> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> >> --- >> drivers/gpu/drm/i915/i915_reg.h | 2 ++ >> drivers/gpu/drm/i915/intel_ddi.c | 30 ++++++++++++++++++++++++++++++ >> drivers/gpu/drm/i915/intel_drv.h | 2 ++ >> 3 files changed, 34 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h >> b/drivers/gpu/drm/i915/i915_reg.h index e85f53cb9cdd..8b1753939299 >> 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -9134,6 +9134,7 @@ enum skl_power_gate { >> #define _DP_TP_CTL_B 0x64140 >> #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) >> #define DP_TP_CTL_ENABLE (1 << 31) >> +#define DP_TP_CTL_FEC_ENABLE (1 << 30) >> #define DP_TP_CTL_MODE_SST (0 << 27) >> #define DP_TP_CTL_MODE_MST (1 << 27) >> #define DP_TP_CTL_FORCE_ACT (1 << 25) >> @@ -9152,6 +9153,7 @@ enum skl_power_gate { >> #define _DP_TP_STATUS_A 0x64044 >> #define _DP_TP_STATUS_B 0x64144 >> #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, >> _DP_TP_STATUS_B) >> +#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) >> #define DP_TP_STATUS_IDLE_DONE (1 << 25) >> #define DP_TP_STATUS_ACT_SENT (1 << 24) >> #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c >> b/drivers/gpu/drm/i915/intel_ddi.c >> index efbada95dc4e..f03f44f332c7 100644 >> --- a/drivers/gpu/drm/i915/intel_ddi.c >> +++ b/drivers/gpu/drm/i915/intel_ddi.c >> @@ -2889,6 +2889,32 @@ static void intel_ddi_clk_disable(struct >intel_encoder *encoder) >> } >> } >> >> +void intel_dp_enable_fec_state(struct intel_dp *intel_dp, >> + const struct intel_crtc_state *crtc_state) > >Can be static. intel_ddi_enable_fec() seems like a better name, and we can just >pass the intel_encoder to this I think. No need to do all the "intel_dp to encoder" >gynmastics then. intel_ddi_enable_fec() is a better name. >> +{ >> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); >> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); >> + enum port port = intel_dig_port->base.port; >> + u32 val; >> + >> + /* FEC support exists for DP 1.4 only */ > >This comment is misleading. There are other reasons besides < DP 1.4 for not >using FEC. IMO just drop the comment. Ok. >> + if (!crtc_state->fec_enable) >> + return; >> + >> + if (!crtc_state->dsc_params.compression_enable) >> + return; > >That check can be removed now. No we will still need this. The fec_enable state is not coupled with compression. So we have to check fec state and the compression .... Anusha >> + >> + val = I915_READ(DP_TP_CTL(port)); >> + val |= DP_TP_CTL_FEC_ENABLE; >> + I915_WRITE(DP_TP_CTL(port), val); >> + >> + if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port), >> + DP_TP_STATUS_FEC_ENABLE_LIVE, >> + DP_TP_STATUS_FEC_ENABLE_LIVE, >> + 1)) >> + DRM_ERROR("Timed out waiting for FEC Enable Status\n"); } >> + >> static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, >> const struct intel_crtc_state *crtc_state, >> const struct drm_connector_state >*conn_state) @@ -2934,9 >> +2960,13 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder >*encoder, >> DP_DECOMPRESSION_EN); >> intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY); >> intel_dp_start_link_train(intel_dp); >> + > >Unrelated whitespace change. > >> if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) >> intel_dp_stop_link_train(intel_dp); >> >> + /* Set FEC state after link training */ > >Redundant comment. > >> + intel_dp_enable_fec_state(intel_dp, crtc_state); >> + >> icl_enable_phy_clock_gating(dig_port); >> >> if (!is_mst) >> diff --git a/drivers/gpu/drm/i915/intel_drv.h >> b/drivers/gpu/drm/i915/intel_drv.h >> index 2a080205968d..1cdfa9c5da43 100644 >> --- a/drivers/gpu/drm/i915/intel_drv.h >> +++ b/drivers/gpu/drm/i915/intel_drv.h >> @@ -1799,6 +1799,8 @@ void >> intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, void >intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, >> const struct intel_crtc_state *crtc_state, >> int state); >> +void intel_dp_enable_fec_state(struct intel_dp *intel_dp, >> + const struct intel_crtc_state *crtc_state); >> void intel_dp_encoder_reset(struct drm_encoder *encoder); void >> intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); void >> intel_dp_encoder_destroy(struct drm_encoder *encoder); >> -- >> 2.17.1 > >-- >Ville Syrjälä >Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
