On Tue, Oct 30, 2018 at 05:45:10PM -0700, Anusha Srivatsa wrote: > With Display Compression, the bit error in the pixel > stream can turn into a significant corruption on > the screen. The DP1.4 adds FEC - Forward Error Correction > scheme which uses Reed-Solomon parity/correction check > generated by the source and used by the sink to detect > and correct small numbers of bit errors in the compressed > stream. > > v2: Avoid doing aux channel read eberytime we check > for FEC support. Instead cache the value of the DPCD > registers, similar to the DSC implementaion (Jani) > > v3: Add fec as a state to crtc. Move around the code. (Ville) > > v4: s/can_fec/fec_enable; s/intel_dp_can_fec/intel_de_supports_fec; > Add intel_dp_source supports_fec() (Ville) One clear thing missing is from this series is the state readout + PIPE_CONF_CHECK > > This is rebased on top of Manasi's End-to-end DSC > Implementation: https://patchwork.freedesktop.org/series/47514/ > > Anusha Srivatsa (7): > i915/dp/fec: Cache the FEC_CAPABLE DPCD register > drm/dp/fec: DRM helper for Forward Error Correction > i915/dp/fec: Check for FEC Support > i915/dp/fec: Add can_fec to the crtc state. > drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION > i915/dp/fec: Configure the Forward Error Correction bits. > drm/i915/fec: Disable FEC state. > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_ddi.c | 60 ++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_dp.c | 58 ++++++++++++++++++++++++++++-- > drivers/gpu/drm/i915/intel_drv.h | 11 ++++++ > include/drm/drm_dp_helper.h | 7 ++++ > 5 files changed, 136 insertions(+), 2 deletions(-) > > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
