On Fri, Oct 26, 2018 at 03:33:37AM +0530, Uma Shankar wrote:
> Defined the plane input csc coefficient registers and macros.
> 6 registers are used to program a total of 9 coefficients,
> added macros to define each of them for all the planes
> supporting the feature on pipes. On ICL, bottom 3 planes
> have this capability.
>
> v2: Segregated the register macro definition as separate patch
> as per Maarten's suggestion.
>
> v3: Removed a redundant 3rd Pipe register definition and
> simplified the equally spaced register definition by adding an
> offset as per Matt's comment.
>
> v4: No Change
>
> Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 69eb573..d806e6b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6569,6 +6569,7 @@ enum {
> #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
> #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> +#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
> #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
> #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
> @@ -6585,6 +6586,55 @@ enum {
> #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> #define _PLANE_NV12_BUF_CFG_2_A 0x70378
>
> +/* Input CSC Register Definitions */
> +#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
> +#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
> +
> +#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
> +#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
> +
> +#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
> + _PLANE_INPUT_CSC_RY_GY_1_B)
> +#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
> + _PLANE_INPUT_CSC_RY_GY_2_B)
> +
> +#define PLANE_INPUT_CSC_COEFF_REG(pipe, plane, index) \
The _REG suffix on these names could probably be dropped to make them a
bit shorter. But otherwise, these match all the offsets I see in the
bspec, so
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
> + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
> +
> +#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
> + _PLANE_INPUT_CSC_PREOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
> + _PLANE_INPUT_CSC_PREOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_PREOFF_REG(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
> + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
> +
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
> +#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
> + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
> +#define PLANE_INPUT_CSC_POSTOFF_REG(pipe, plane, index) \
> + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
> + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
>
> #define _PLANE_CTL_1_B 0x71180
> #define _PLANE_CTL_2_B 0x71280
> --
> 1.9.1
>
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--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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