On Wed, Oct 24, 2018 at 03:28:37PM -0700, Manasi Navare wrote:
> 1. Disable Left/right VDSC branch in DSS Ctrl reg
> depending on the number of VDSC engines being used
> 2. Disable joiner in DSS Ctrl reg
>
> v3 (From Manasi):
> * Add Disable PG2 for VDSC on eDP
> v2 (From Manasi):
> * Use old_crtc_state to find dsc params
> * Add a condition to disable only if
> dsc state compression is enabled
> * Use correct DSS CTL regs
>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++
> drivers/gpu/drm/i915/intel_vdsc.c | 33 ++++++++++++++++++++++++++++
> 3 files changed, 48 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 16e6bb98eb1b..e31f19a688bc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3489,6 +3489,8 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
> bool enable);
> extern void intel_dsc_enable(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> +extern void intel_dsc_disable(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state);
>
> int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 023a9baef101..3d9d70d3314e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5853,6 +5853,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> + struct drm_connector_state *conn_state;
> + struct drm_connector *conn;
> + int i;
>
> intel_encoders_disable(crtc, old_crtc_state, old_state);
>
> @@ -5869,6 +5872,16 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
> if (!transcoder_is_dsi(cpu_transcoder))
> intel_ddi_disable_transcoder_func(old_crtc_state);
>
> + for_each_new_connector_in_state(old_state, conn, conn_state, i) {
> + struct intel_encoder *encoder =
> + to_intel_encoder(conn_state->best_encoder);
> +
> + if (conn_state->crtc != crtc)
> + continue;
> +
> + intel_dsc_disable(encoder, old_crtc_state);
> + }
Can't we do this from the encodr hooks? /me didn't check the modeset
sequence docs...
> +
> if (INTEL_GEN(dev_priv) >= 9)
> skylake_scaler_disable(intel_crtc);
> else
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index 8b46619aae15..5e76b4a44d90 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -1042,3 +1042,36 @@ void intel_dsc_enable(struct intel_encoder *encoder,
>
> return;
> }
> +
> +void intel_dsc_disable(struct intel_encoder *encoder,
> + struct intel_crtc_state *old_crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + enum pipe pipe = crtc->pipe;
> + i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> + u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
> +
> + if (!old_crtc_state->dsc_params.compression_enable)
> + return;
> +
> + if (encoder->type == INTEL_OUTPUT_EDP) {
> + dss_ctl1_reg = DSS_CTL1;
> + dss_ctl2_reg = DSS_CTL2;
> + } else {
> + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
> + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
> + }
> + dss_ctl1_val = I915_READ(dss_ctl1_reg);
> + if (dss_ctl1_val & JOINER_ENABLE)
> + dss_ctl1_val &= ~JOINER_ENABLE;
> + I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
> +
> + dss_ctl2_val = I915_READ(dss_ctl2_reg);
> + if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
> + dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
> + dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
> + RIGHT_BRANCH_VDSC_ENABLE);
> + I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
> +
> +}
> --
> 2.18.0
--
Ville Syrjälä
Intel
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