Quoting Zhang, Xiong Y (2018-10-19 11:11:23)
> > Quoting Zhenyu Wang (2018-10-19 04:05:20)
> > > On 2018.10.18 13:40:31 +0800, Xiong Zhang wrote:
> > > > Currently the guest couldn't boot up under GVT-g environment as the
> > > > following call trace exists:
> > > > [ 272.504762] BUG: unable to handle kernel NULL pointer dereference
> > > > at 0000000000000100 [ 272.504834] Call Trace:
> > > > [ 272.504852] execlists_context_pin+0x2b2/0x520 [i915] [
> > > > 272.504869] intel_gvt_scan_and_shadow_workload+0x50/0x4d0 [i915]
> > [
> > > > 272.504887] intel_vgpu_create_workload+0x3e2/0x570 [i915] [
> > > > 272.504901] intel_vgpu_submit_execlist+0xc0/0x2a0 [i915] [
> > > > 272.504916] elsp_mmio_write+0xc7/0x130 [i915] [ 272.504930]
> > > > intel_vgpu_mmio_reg_rw+0x24a/0x4c0 [i915] [ 272.504944]
> > > > intel_vgpu_emulate_mmio_write+0xac/0x240 [i915] [ 272.504947]
> > > > intel_vgpu_rw+0x22d/0x270 [kvmgt] [ 272.504949]
> > > > intel_vgpu_write+0x164/0x1f0 [kvmgt]
> > > >
> > > > GVT GEM context is created by i915_gem_context_create_gvt() which
> > > > doesn't allocate ppgtt. So GVT GEM context structure doesn't have a
> > > > valid i915_hw_ppgtt.
> > > >
> > > > This patch create ppgtt table at GVT GEM context creation, then
> > > > assign shadow ppgtt's root table address to this ppgtt when shadow
> > > > ppgtt will be used on GPU. So GVT GEM context has valid ppgtt
> > > > address. But note that this ppgtt only contain valid ppgtt root
> > > > table address, the table entry in this ppgtt structure are invalid.
> > > >
> > > > Fixes:4a3d3f6785be("drm/i915: Match code to comment and enforce
> > > > ppgtt for execlists")
> > > >
> > > > Signed-off-by: Xiong Zhang <xiong.y.zhang@xxxxxxxxx>
> > > > Reviewed-by: Zhenyu Wang <zhenyuw@xxxxxxxxxxxxxxx>
> > >
> > > Any more comment for this? We need it for current gvt broken on
> > > drm-tip, and it requires to change i915 for gvt ppgtt allocation, so I
> > > assume it's better to be merged by i915 directly, or do you like a gvt pull
> > instead?
> >
> > You only needed ctx->ppgtt being set I thought, as you previously ignored
> > the initial PD bits in the context image and overwrote the registers anyway.
> >
> > Do you want what appears to be a significant change to gvt itself to enter
> > from i915?
> [Zhang, Xiong Y] For 48 bit guest ppgtt, we only need ctx->ppgtt being set.
> But for 32 bit guest ppgtt, i915 call execlists_update_context_pdps() which is behind gvt pdp updates, if ctx->ppgtt isn't correct, 32bit ppgtt guest will be broken.
The code implies that gvt doesn't support 32b guests.
-Chris
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