== Series Details == Series: drm/i915/icl: dsi enabling (rev2) URL : https://patchwork.freedesktop.org/series/51011/ State : warning == Summary == $ dim checkpatch origin/drm-tip c25368a8ec1e drm/i915: make encoder enable and disable hooks optional -:44: WARNING:LONG_LINE: line over 100 characters #44: FILE: drivers/gpu/drm/i915/intel_display.c:15448: + encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); total: 0 errors, 1 warnings, 0 checks, 61 lines checked f9a6a6ec351f drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init() -:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #30: new file mode 100644 -:114: WARNING:LONG_LINE: line over 100 characters #114: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:552: + intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); total: 0 errors, 2 warnings, 0 checks, 118 lines checked efa9b026e207 drm/i915/dsi: abstract dphy parameter init -:130: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #130: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:691: + pixel_format_from_register_bits( -:156: WARNING:BRACES: braces {} are not necessary for single statement blocks #156: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:717: + if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { + intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); + } -:157: WARNING:LONG_LINE: line over 100 characters #157: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:718: + intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); -:165: CHECK:BRACES: braces {} should be used on all arms of this statement #165: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:726: + if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { [...] + } else [...] -:174: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #174: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:735: + burst_mode_ratio = DIV_ROUND_UP( -:183: CHECK:BRACES: Unbalanced braces around else statement #183: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:744: + } else total: 0 errors, 2 warnings, 4 checks, 169 lines checked 0b6b3d7d10f9 drm/i915/dsi: abstract intel_dsi_tlpx_ns() 4ea7560e8bf0 drm/i915/icl: Make common DSI functions available 8dd4accf0f08 drm/i915/icl: Program DSI clock and data lane timing params 3887d2f3fc66 drm/i915/icl: Program TA_TIMING_PARAM registers d45e6957f8bc drm/i915/icl: Get DSI transcoder for a given port 82e9c3ba9891 drm/i915/icl: Add macros for MMIO of DSI transcoder registers c6be44e9b750 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register d9fddc1fdb98 drm/i915/icl: Configure DSI transcoders -:146: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 #146: FILE: drivers/gpu/drm/i915/intel_dsi.h:85: + bool bgr_enabled; total: 0 errors, 0 warnings, 1 checks, 121 lines checked 3b0bc52936dc drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers 3a6e7dbce100 drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers c13805c69a43 drm/i915/icl: Define DSI transcoder timing registers 27b32fd273e3 drm/i915/icl: Configure DSI transcoder timings d52459f4c75c drm/i915/icl: Define TRANS_CONF register for DSI 952873ccf0b2 drm/i915/icl: Enable DSI transcoders fd4c6e67e010 drm/i915/icl: Define DSI panel programming registers cdece01f26bf drm/i915/icl: Set max return packet size for DSI panel 894c9626886b drm/i915/icl: Power on DSI panel b2d70882145b drm/i915/icl: Wait for header/payload credits release -:22: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #22: FILE: drivers/gpu/drm/i915/icl_dsi.c:31: +static void __attribute__((unused)) wait_for_dsi_hdr_credit_release( -:34: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #34: FILE: drivers/gpu/drm/i915/icl_dsi.c:43: +static void __attribute__((unused)) wait_for_dsi_payload_credit_release( total: 0 errors, 0 warnings, 2 checks, 30 lines checked 07124f12764f drm/i915/icl: Ensure all cmd/data disptached to panel 8a33c1840e00 drm/i915/icl: Turn ON panel backlight _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
