This u32 pv_caps field is used to control the different
level pvmmio feature for MMIO emulation in GVT.
This field is default zero, no pvmmio feature enabled.
it also add VGT_CAPS_PVMMIO capability BIT for guest to check GVTg
can support PV feature or not.
v1: addressed RFC comment to remove enable_pvmmio module parameter
by pv capability check.
v0: RFC, introudced enable_pvmmio module parameter.
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 11 +++++++++++
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/i915_pvinfo.h | 17 ++++++++++++++++-
drivers/gpu/drm/i915/i915_vgpu.c | 19 +++++++++++++++++--
4 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 794a8a0..d22154a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -56,6 +56,7 @@
#include "i915_params.h"
#include "i915_reg.h"
+#include "i915_pvinfo.h"
#include "i915_utils.h"
#include "intel_bios.h"
@@ -1343,6 +1344,7 @@ struct i915_workarounds {
struct i915_virtual_gpu {
bool active;
u32 caps;
+ u32 pv_caps;
};
/* used in computing the new watermarks state */
@@ -2853,6 +2855,11 @@ static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
return dev_priv->vgpu.active;
}
+static inline bool intel_vgpu_has_pvmmio(struct drm_i915_private *dev_priv)
+{
+ return dev_priv->vgpu.caps & VGT_CAPS_PVMMIO;
+}
+
u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
enum pipe pipe);
void
@@ -3880,4 +3887,8 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
return I915_HWS_CSB_WRITE_INDEX;
}
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level) \
+ (intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+ && (dev_priv->vgpu.pv_caps & level))
+
#endif
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..cc2b2f5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -67,7 +67,7 @@ struct drm_printer;
param(bool, nuclear_pageflip, false) \
param(bool, enable_dp_mst, true) \
param(bool, enable_dpcd_backlight, false) \
- param(bool, enable_gvt, false)
+ param(bool, enable_gvt, false) \
#define MEMBER(T, member, ...) T member;
struct i915_params {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d5..26709e8 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,12 +49,26 @@ enum vgt_g2v_type {
VGT_G2V_MAX,
};
+#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
+
/*
* VGT capabilities type
*/
#define VGT_CAPS_FULL_48BIT_PPGTT BIT(2)
#define VGT_CAPS_HWSP_EMULATION BIT(3)
#define VGT_CAPS_HUGE_GTT BIT(4)
+#define VGT_CAPS_PVMMIO BIT(5)
+
+/*
+ * define different levels of PVMMIO optimization
+ */
+enum pvmmio_levels {
+ PVMMIO_ELSP_SUBMIT = 0x1,
+ PVMMIO_PLANE_UPDATE = 0x2,
+ PVMMIO_PLANE_WM_UPDATE = 0x4,
+ PVMMIO_MASTER_IRQ = 0x8,
+ PVMMIO_PPGTT_UPDATE = 0x10,
+};
struct vgt_if {
u64 magic; /* VGT_MAGIC */
@@ -106,8 +120,9 @@ struct vgt_if {
u32 execlist_context_descriptor_lo;
u32 execlist_context_descriptor_hi;
+ u32 enable_pvmmio;
- u32 rsv7[0x200 - 24]; /* pad to one page */
+ u32 rsv7[0x200 - 25]; /* pad to one page */
} __packed;
#define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a..907bbd2 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -76,9 +76,24 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
}
dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
-
dev_priv->vgpu.active = true;
- DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+
+ if (!intel_vgpu_has_pvmmio(dev_priv)) {
+ DRM_INFO("Virtual GPU for Intel GVT-g detected\n");
+ return;
+ }
+
+ /* If guest wants to enable pvmmio, it needs to enable it explicitly
+ * through vgt_if interface, and then read back the enable state from
+ * gvt layer.
+ */
+ __raw_i915_write32(dev_priv, vgtif_reg(enable_pvmmio),
+ dev_priv->vgpu.pv_caps);
+ dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
+ vgtif_reg(enable_pvmmio));
+
+ DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+ dev_priv->vgpu.pv_caps);
}
bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
