On Thu, Oct 04, 2018 at 03:43:49PM +0300, Stanislav Lisovskiy wrote:
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
>
> v2: Edited commit message, removed redundant whitespaces.
>
> v3: Fixed fallthrough logic for the format switch cases.
>
> v4: Yet again fixed fallthrough logic, to reuse code from other case
> labels.
>
> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
>
> v6: Removed unneeded initializer for new XYUV format.
>
> v7: Added scaling support for DRM_FORMAT_XYUV
>
> v8: Edited commit message to be more clear about skl+, renamed
> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> doesn't support per-pixel alpha. Fixed minor code issues.
>
> v9: Moved DRM format check to proper place in intel_framebuffer_init.
>
> v10: Added missing XYUV format to sprite planes for skl+.
>
> v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV8888.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
Looks good to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Though one thing we probably want to do still is adjust
intel_plane_check_src_coordinates() to allow odd coordinates for
this format. I think we should be able to just replace those
hardcoded numbers in there with fb->format->[hv]sub and it should
just work (tm).
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/intel_sprite.c | 3 +++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 09bc8e730ee1..ac24ac4b1d51 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6501,7 +6501,7 @@ enum {
> #define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24)
> #define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24)
> #define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
> -#define PLANE_CTL_FORMAT_AYUV (8 << 24)
> +#define PLANE_CTL_FORMAT_XYUV (8 << 24)
> #define PLANE_CTL_FORMAT_INDEXED (12 << 24)
> #define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
> #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b2bab57cd113..9e65c47f3f4c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -87,6 +87,7 @@ static const uint32_t skl_primary_formats[] = {
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV8888,
> };
>
> static const uint32_t skl_pri_planar_formats[] = {
> @@ -102,6 +103,7 @@ static const uint32_t skl_pri_planar_formats[] = {
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV8888,
> DRM_FORMAT_NV12,
> };
>
> @@ -2673,6 +2675,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_XYUV:
> + return DRM_FORMAT_XYUV8888;
> default:
> case PLANE_CTL_FORMAT_XRGB_8888:
> if (rgb_order) {
> @@ -3502,6 +3506,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_XRGB_2101010;
> case DRM_FORMAT_XBGR2101010:
> return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> + case DRM_FORMAT_XYUV8888:
> + return PLANE_CTL_FORMAT_XYUV;
> case DRM_FORMAT_YUYV:
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> case DRM_FORMAT_YVYU:
> @@ -4960,6 +4966,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV8888:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13421,6 +13428,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV8888:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
> @@ -14545,6 +14553,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> goto err;
> }
> break;
> + case DRM_FORMAT_XYUV8888:
> + if (INTEL_GEN(dev_priv) < 9) {
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> + drm_get_format_name(mode_cmd->pixel_format, &format_name));
> + goto err;
> + }
> + break;
> case DRM_FORMAT_YUYV:
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_YVYU:
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 9600ccfc5b76..dec7546446d5 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1266,6 +1266,7 @@ static uint32_t skl_plane_formats[] = {
> DRM_FORMAT_YVYU,
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV8888,
> };
>
> static uint32_t skl_planar_formats[] = {
> @@ -1279,6 +1280,7 @@ static uint32_t skl_planar_formats[] = {
> DRM_FORMAT_UYVY,
> DRM_FORMAT_VYUY,
> DRM_FORMAT_NV12,
> + DRM_FORMAT_XYUV8888,
> };
>
> static const uint64_t skl_plane_format_modifiers_noccs[] = {
> @@ -1420,6 +1422,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV8888:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
> --
> 2.17.1
>
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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--
Ville Syrjälä
Intel
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