From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
ILK already has the watermark registers for the LP3 level so
bump num_levels to 4. The BIOS still does not provide memory
latency values for for LP3 though so it will not be used
unless the latency values are overridden via debugfs.
This also requires that we check for latency==0 zero when
computing the watermarks so that we keep disabling any wm
level which isn't supposed to be used. The behaviour now matches
that of the g4x/vlv wm code.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7bd29bba81c1..dd5edd984fb5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2537,6 +2537,9 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
uint32_t method1, method2;
int cpp;
+ if (latency == 0)
+ return USHRT_MAX;
+
if (!intel_wm_plane_visible(cstate, pstate))
return 0;
@@ -2564,6 +2567,9 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
uint32_t method1, method2;
int cpp;
+ if (latency == 0)
+ return USHRT_MAX;
+
if (!intel_wm_plane_visible(cstate, pstate))
return 0;
@@ -2585,6 +2591,9 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
int latency = intel_plane_wm_latency(plane, level);
int cpp;
+ if (latency == 0)
+ return USHRT_MAX;
+
if (!intel_wm_plane_visible(cstate, pstate))
return 0;
@@ -2953,10 +2962,8 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
{
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
dev_priv->wm.num_levels = 5;
- else if (INTEL_GEN(dev_priv) >= 6)
- dev_priv->wm.num_levels = 4;
else
- dev_priv->wm.num_levels = 3;
+ dev_priv->wm.num_levels = 4;
ilk_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
ilk_fixup_wm_latency_units(dev_priv, dev_priv->wm.pri_latency);
--
2.18.1
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