On Wed, Oct 03, 2018 at 03:37:08PM +0200, Maarten Lankhorst wrote:
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 17 +++++++++--------
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 56784ae26369..36a8d5fb8881 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1565,14 +1565,15 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
> }
> }
>
> -static void i9xx_disable_pll(struct intel_crtc *crtc)
> +static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
>
> /* Disable DVO 2x clock on both PLLs if necessary */
> if (IS_I830(dev_priv) &&
> - intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
> + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO) &&
> !intel_num_dvo_pipes(dev_priv)) {
> I915_WRITE(DPLL(PIPE_B),
> I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
> @@ -4323,10 +4324,10 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
> DRM_DEBUG_KMS("FDI train done.\n");
> }
Looks like you missed i9xx_set_pll_dividers() here. I think I saw it in
a later patch though, but maybe move it here?
commit msg...
Otherwise
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> -static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
> +static void ironlake_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = intel_crtc->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> int pipe = intel_crtc->pipe;
> i915_reg_t reg;
> u32 temp;
> @@ -4335,7 +4336,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
> - temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
> + temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
> temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
> I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
>
> @@ -5614,7 +5615,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
> /* Note: FDI PLL enabling _must_ be done before we enable the
> * cpu pipes, hence this is separate from all the other fdi/pch
> * enabling. */
> - ironlake_fdi_pll_enable(intel_crtc);
> + ironlake_fdi_pll_enable(pipe_config);
> } else {
> assert_fdi_tx_disabled(dev_priv, pipe);
> assert_fdi_rx_disabled(dev_priv, pipe);
> @@ -6211,7 +6212,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> else if (IS_VALLEYVIEW(dev_priv))
> vlv_disable_pll(dev_priv, pipe);
> else
> - i9xx_disable_pll(intel_crtc);
> + i9xx_disable_pll(old_crtc_state);
> }
>
> intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
> --
> 2.19.0
>
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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