From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Keep a per-engine number of runnable (waiting for GPU time) requests.
We choose to mange the runnable counter at the backend level instead of at
the request submit_notify callback. The latter would be more consolidated
and less code, but it would require making the counter either atomic_t or
taking the engine->timeline->lock in submit_notify. So the choice is to do
it at the backend level for the benefit of fewer atomic instructions.
v2:
* Move queued increment from insert_request to execlist_submit_request to
avoid bumping when re-ordering for priority.
* Support the counter on the ringbuffer submission path as well, albeit
just notionally. (Chris Wilson)
v3:
* Rebase.
v4:
* Rename and move the stats into a container structure. (Chris Wilson)
v5:
* Re-order fields in struct intel_engine_cs. (Chris Wilson)
v6-v8:
* Rebases.
v9:
* Fix accounting during wedging.
v10:
* Improved commit message. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_request.c | 7 +++++++
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++--
drivers/gpu/drm/i915/intel_lrc.c | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.h | 9 +++++++++
5 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7d45e71100bc..d3a730f6ef65 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3309,6 +3309,7 @@ static void nop_complete_submit_request(struct i915_request *request)
dma_fence_set_error(&request->fence, -EIO);
spin_lock_irqsave(&request->engine->timeline.lock, flags);
+ request->engine->request_stats.runnable++;
__i915_request_submit(request);
intel_engine_init_global_seqno(request->engine, request->global_seqno);
spin_unlock_irqrestore(&request->engine->timeline.lock, flags);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index abd4dacbab8e..689f838e849c 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -457,6 +457,9 @@ void __i915_request_submit(struct i915_request *request)
/* Transfer from per-context onto the global per-engine timeline */
move_to_timeline(request, &engine->timeline);
+ GEM_BUG_ON(engine->request_stats.runnable == 0);
+ engine->request_stats.runnable--;
+
trace_i915_request_execute(request);
wake_up_all(&request->execute);
@@ -470,6 +473,8 @@ void i915_request_submit(struct i915_request *request)
/* Will be called from irq-context when using foreign fences. */
spin_lock_irqsave(&engine->timeline.lock, flags);
+ engine->request_stats.runnable++;
+
__i915_request_submit(request);
spin_unlock_irqrestore(&engine->timeline.lock, flags);
@@ -507,6 +512,8 @@ void __i915_request_unsubmit(struct i915_request *request)
/* Transfer back from the global per-engine timeline to per-context */
move_to_timeline(request, request->timeline);
+ engine->request_stats.runnable++;
+
/*
* We don't need to wake_up any waiters on request->execute, they
* will get woken by any other event or us re-adding this request
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 1c6143bdf5a4..f46ef765aed0 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1460,11 +1460,12 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (i915_terminally_wedged(&engine->i915->gpu_error))
drm_printf(m, "*** WEDGED ***\n");
- drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n",
+ drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], runnable %u\n",
intel_engine_get_seqno(engine),
intel_engine_last_submit(engine),
engine->hangcheck.seqno,
- jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
+ jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp),
+ engine->request_stats.runnable);
drm_printf(m, "\tReset count: %d (global %d)\n",
i915_reset_engine_count(error, engine),
i915_reset_count(error));
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 28d56387edf5..f0c2673fce49 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1023,6 +1023,7 @@ static void queue_request(struct intel_engine_cs *engine,
int prio)
{
list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio));
+ engine->request_stats.runnable++;
}
static void __submit_queue_imm(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 7078132fc631..07491b6c7796 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -380,6 +380,15 @@ struct intel_engine_cs {
struct drm_i915_gem_object *default_state;
void *pinned_default_state;
+ struct {
+ /**
+ * @runnable: Number of runnable requests sent to the backend.
+ *
+ * Count of requests waiting for the GPU to execute them.
+ */
+ unsigned int runnable;
+ } request_stats;
+
unsigned long irq_posted;
#define ENGINE_IRQ_BREADCRUMB 0
--
2.17.1
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