Quoting Xiaolin Zhang (2018-09-27 19:37:45) > To improve GVTg performance, it could reduce the mmio access trap > numbers within guest driver in some certain scenarios since mmio > access trap will introuduce vm exit/vm enter cost. > > the solution in this patch set is to setup a shared memory region > which accessed both by guest and GVTg without trap cost. the shared > memory region is allocated by guest driver and guest driver will > pass the region's memory guest physical address to GVTg through > PVINFO register and later GVTg can access this region directly without > trap cost to achieve data exchange purpose between guest and GVTg. > > in this patch set, 3 kind of pvmmio optimization implemented which is > controlled by enable_pvmmio PVINO register with different level flag. > 1. workload submission (context submission): reduce 4 traps to 1 trap. > 2. master irq: reduce 2 traps to 1 trap. > 3. ppgtt update: eliminate the cost of ppgtt write protection. > > based on the experiment, the performance was gained 4 percent (average) > improvment with regard to both media and 3D workload benchmarks. > > based on the pvmmio framework, it could achive more sceneario optimization > such as globle GTT update, display plane and water mark update with guest. Overall comments: The patches should be properly prefixed and split down. We should have "drm/i915:" patches that touch i915 portions, and those should not touch any gvt parts. Then there should be "drm/i915/gvt:" parts which don't touch anything from i915, and would be reviewed in the GVT list. We'd then proceed to merge the i915 changes and the GVT changes would be merged in the GVT tree. Regards, Joonas _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
