Quoting Tvrtko Ursulin (2018-09-14 17:09:27)
> From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
>
> Configuring RPCS in context image just before pin is sufficient and will
> come extra handy in one of the following patches.
>
> v2:
> * Split image setup a bit differently. (Chris Wilson)
>
> v3:
> * Update context image after reset as well - otherwise the application
> of pinned default state clears the RPCS.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> Suggested-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> # v2
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 47 ++++++++++++++++++++------------
> 1 file changed, 30 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index a51be16ddaac..4fcff1be91c9 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1305,6 +1305,26 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
> return i915_vma_pin(vma, 0, 0, flags);
> }
>
> +static u32 make_rpcs(struct drm_i915_private *dev_priv);
> +
> +static void
> +__execlists_update_reg_state(struct intel_engine_cs *engine,
> + struct intel_context *ce)
> +{
> + u32 *regs = ce->lrc_reg_state;
> + struct intel_ring *ring = ce->ring;
> +
> + regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(ring->vma);
> + regs[CTX_RING_HEAD + 1] = ring->head;
> + regs[CTX_RING_TAIL + 1] = ring->tail;
> +
> + /* RPCS */
> + if (engine->class == RENDER_CLASS) {
> + ce->lrc_reg_state[CTX_R_PWR_CLK_STATE + 1] =
> + make_rpcs(engine->i915);
regs[CTX_R_PWR_CLK_STATE + 1] = make_rpcs(engine->i915);
Looks like the plan is coming together.
-Chris
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