On Fri, Sep 14, 2018 at 02:16:12PM +0100, Chris Wilson wrote: > Quoting Ville Syrjälä (2018-09-14 14:03:35) > > On Fri, Sep 14, 2018 at 10:42:15AM +0100, Chris Wilson wrote: > > > That we use a WB mapping for updating the RING_TAIL register inside the > > > context image even on !llc machines has been a source of consternation > > > for every reader. It appears to work on bsw+, but it may just have been > > > that we have been incredibly bad at detecting the errors. > > > > Presumably it's due to the "all ggtt accesses go through pat[0]" and > > we make pat[0] snoop. So presumably the hw should snoop when loading > > the context... maybe. > > Shows how much attention I pay, I thought we made pat[0] uncached. Seems > strange to suggest that we should always be snooping when reading GGTT > from the GPU. IIRC I did it originally that way for the status page. Sadly it's either "all snooped" or "none snooped" due to the hw not having wired up the bits for ggtt. > > We still have the same PTE bits for GGTT as for ppGTT, do we not? Same, except the pwt/pcd/pat bits do nothing for ggtt. -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
