On Fri, Sep 14, 2018 at 11:42:33AM +0530, Madhav Chauhan wrote:
> On 9/12/2018 11:30 PM, Ville Syrjälä wrote:
> > On Wed, Sep 12, 2018 at 03:06:41PM +0530, Madhav Chauhan wrote:
> >> On 7/19/2018 9:52 PM, Ville Syrjälä wrote:
> >>> On Tue, Jul 10, 2018 at 03:10:12PM +0530, Madhav Chauhan wrote:
> >>>> This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
> >>>> DSI transcoder registers.
> >>>>
> >>>> Credits-to: Jani N
> >>>>
> >>>> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> >>>> Signed-off-by: Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
> >>>> ---
> >>>> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> >>>> 1 file changed, 5 insertions(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>>> index 1d13ba9..62bc76e 100644
> >>>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>>> @@ -9576,6 +9576,11 @@ enum skl_power_gate {
> >>>> #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
> >>>> #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
> >>>>
> >>>> +/* gen11 DSI */
> >>>> +#define _DSI_TRANS(tc, dsi0, dsi1) (((tc) == TRANSCODER_DSI_0) ? \
> >>>> + (dsi0) : (dsi1))
> >>> _PIPE() etc. should result in slughtly better code IIRC.
> >> Can you please clarify on this??
> > Plenty of examples in i915_reg.h for using _PIPE().
>
> I meant what are advantages of using _PIPE against the current approach??
Uniform style, better generated code usually (look at the generated asm
to verify).
>
> Also if we use _PIPE, are you suggesting something below:
> #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_PIPE(tc, dsi0, dsi1))
> Using above macro we will get wrong DSI addresses as TRANS_DSI_0 value is 5.
(tc)-TRANSCODER_DSI_0
>
> Or do you mean to use PORT instead of TRANS_DSI_0/1 to _MMIO_DSI??
>
> Regards,
> Madhav
>
> >
> >> Regards,
> >> Madhav
> >>
> >>>> +#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO(_DSI_TRANS(tc, dsi0, dsi1))
> >>>> +
> >>>> #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
> >>>> #define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
> >>>> #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
> >>>> --
> >>>> 2.7.4
> >>>>
> >>>> _______________________________________________
> >>>> Intel-gfx mailing list
> >>>> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> >>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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