On Tue, 2018-07-10 at 15:10 +0530, Madhav Chauhan wrote:
> This patch set the loadgen select and latency optimization for
> aux and transmit lanes of combo phy transmitters. It will be
> used for MIPI DSI HS operations.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 38
> ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> b/drivers/gpu/drm/i915/icl_dsi.c
> index 13830e4..a571339 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -105,10 +105,48 @@ static void gen11_dsi_power_up_lanes(struct
> intel_encoder *encoder)
> }
> }
>
> +static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
> *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder-
> >base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
> >base);
> + enum port port;
> + u32 tmp;
> + int lane;
> +
> + /* Step 4b(i) set loadgen select for transmit and aux lanes
> */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> + tmp &= ~LOADGEN_SELECT;
> + I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> + for (lane = 0; lane <= 3; lane++) {
> + tmp = I915_READ(ICL_PORT_TX_DW4_LN(port,
> lane));
> + tmp &= ~LOADGEN_SELECT;
> + if (lane != 2)
> + tmp |= LOADGEN_SELECT;
> + I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane),
> tmp);
> + }
> + }
> +
> + /* Step 4b(ii) set latency optimization for transmit and aux
> lanes */
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> + tmp &= ~FRC_LATENCY_OPTIM_MASK;
> + tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> + I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> + tmp &= ~FRC_LATENCY_OPTIM_MASK;
> + tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> + I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> + }
> +}
>
I think bspec states that latency optimization should be set only for
Transmit lanes 0, 1, 3. Is it fine to use a group access(i.e
ICL_PORT_TX_DW2_GRP) here? I think it states also that no latency
optimization is needed for the clock lane.
--
Best Regards,
Lisovskiy Stanislav
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