From: Kai Chen <kai.chen@xxxxxxxxx>
On GEN9LP, raise the RPS FUp Interrupt Limiter above softmax so that the
HW won't miss interrupt when requested max_freq is set back to RP0
value.
The (v2) is to explain a bit more detail background about the change in
the code.
Signed-off-by: Kai Chen <kai.chen@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d99e5fabe93c..6574696b83cb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6276,7 +6276,27 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
* frequency, if the down threshold expires in that window we will not
* receive a down interrupt. */
if (INTEL_GEN(dev_priv) >= 9) {
- limits = (rps->max_freq_softlimit) << 23;
+ int max_freq = rps->max_freq_softlimit;
+ int rp0_freq = rps->rp0_freq;
+
+ if (IS_GEN9_LP(dev_priv) && (max_freq == rp0_freq))
+ /* For GEN9_LP, the HW seems insensitive to the RP FUp
+ * interrupt limiter threshold by design. This symptom
+ * is experienced in the IGT test (pm_rps): when the
+ * test sets the max_freq back to RP0, the interrupt
+ * limits register is also programmed to the max_freq
+ * per design. But as a result, the actual freq is not
+ * the max_freq detected. It is suggested (based on the
+ * best test/tuning practice) to increase the upper
+ * interrupt limiter just by 1 (16.6MHz) so that the HW
+ * will generate an interrupt when we are near or just
+ * below the upper limit.
+ */
+
+ limits = (rps->max_freq_softlimit + 1) << 23;
+ else
+ limits = (rps->max_freq_softlimit) << 23;
+
if (val <= rps->min_freq_softlimit)
limits |= (rps->min_freq_softlimit) << 14;
} else {
--
2.17.1
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