== Series Details == Series: Per context dynamic (sub)slice power-gating (rev2) URL : https://patchwork.freedesktop.org/series/48194/ State : warning == Summary == $ dim checkpatch origin/drm-tip ed66235dc3a5 drm/i915/execlists: Move RPCS setup to context pin ecdf22ac2704 drm/i915: Program RPCS for Broadwell 377a656e5c19 drm/i915: Record the sseu configuration per-context & engine 3a30bf8ddfa7 drm/i915/perf: lock powergating configuration to default when active 51555815cbdc drm/i915: Add timeline barrier support 8a0c3e82be78 drm/i915: Expose RPCS (SSEU) configuration to userspace -:40: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #40: v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel) total: 0 errors, 1 warnings, 0 checks, 441 lines checked 8e7f97c0a4d7 drm/i915/icl: Support co-existance between per-context SSEU and OA -:4: WARNING:TYPO_SPELLING: 'existance' may be misspelled - perhaps 'existence'? #4: Subject: [PATCH] drm/i915/icl: Support co-existance between per-context SSEU total: 0 errors, 1 warnings, 0 checks, 33 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
