== Series Details == Series: New GuC ABI (resend for CI) URL : https://patchwork.freedesktop.org/series/48896/ State : warning == Summary == $ dim checkpatch origin/drm-tip 01e55a38a7a5 drm/i915/guc: Update GuC power domain states 3b815ce8b593 drm/i915/guc: Don't allow GuC submission on pre-Gen11 -:55: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' #55: FILE: drivers/gpu/drm/i915/intel_uc.c:304: if (USES_GUC_SUBMISSION(i915)) { + total: 0 errors, 0 warnings, 1 checks, 33 lines checked a735c876fa91 drm/i915/guc: Simplify preparation of GuC parameter block 12348d2284cf drm/i915/guc: Support dual Gen9/Gen11 parameters block 327d94bb826d drm/i915/guc: Update sample-forcewake command d123446c4cff drm/i915/guc: Use guc_class instead of engine_class in fw interface 2496963c4c95 drm/i915/guc: New GuC ADS object definition b81cf8399904 drm/i915/guc: Make use of the SW counter field in the context descriptor 0b01bfddfd3a drm/i915/guc: New GuC IDs based on engine class and instance 20726185b3e4 drm/i915: Add hooks for (per-engine) context allocation/update/free b01e1377dd0c drm/i915/guc: New GuC stage descriptors -:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bit' - possible side-effects? #60: FILE: drivers/gpu/drm/i915/i915_utils.h:121: +#define bitmap32_test_bit(bitmap, bit) ({ \ + (bitmap)[(bit) / 32] & (1 << ((bit) % 32)); \ +}) -:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bit' - possible side-effects? #64: FILE: drivers/gpu/drm/i915/i915_utils.h:125: +#define bitmap32_set_bit(bitmap, bit) ({ \ + (bitmap)[(bit) / 32] |= (1 << ((bit) % 32)); \ +}) -:68: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bit' - possible side-effects? #68: FILE: drivers/gpu/drm/i915/i915_utils.h:129: +#define bitmap32_clear_bit(bitmap, bit) ({ \ + (bitmap)[(bit) / 32] &= ~(1 << ((bit) % 32)); \ +}) total: 0 errors, 0 warnings, 3 checks, 431 lines checked 8f2bf1cb4482 drm/i915/guc: New GuC workqueue item submission mechanism 564d1d6d7668 drm/i915/guc: Add support for resume-parsing wq item 5c944095a7d0 drm/i915/guc: New reset-engine command ba14d4829a19 drm/i915/guc: Support for extended GuC notification messages 68f8b241aa86 drm/i915/guc: New engine-reset-complete message 847af02ce83a drm/i915/guc: New GuC interrupt register for Gen11 b553a7d7d5c1 drm/i915/guc: New GuC scratch registers for Gen11 551ffda09be5 drm/i915/huc: New HuC status register for Gen11 a5473e9796c9 drm/i915/guc: Enable command transport buffers for Gen11 b87adae1c3d3 HAX Don't enable GuC submission on pre-Gen11 even if forced _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
