On Tue, Aug 28, 2018 at 06:32:01PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll > mgr into the clock readout function as well. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722 > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index f3b115ce4029..68b301e6f41d 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1416,6 +1416,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, > > ref_clock = dev_priv->cdclk.hw.ref; could we move this up to the beginning of the function and then reuse that if (INTEL_GEN(dev_priv) >= 11) { block? Anyway, this change is needed and right so however you decide to proceed: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > > + /* > + * For ICL, the spec states: if reference frequency is 38.4, use 19.2 > + * because the DPLL automatically divides that by 2. > + */ > + if (IS_ICELAKE(dev_priv) && ref_clock == 38400) > + ref_clock = 19200; > + > dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock; > > dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> > -- > 2.16.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
