On Tue, Aug 28, 2018 at 02:52:20PM +0300, Imre Deak wrote: > On Tue, Aug 28, 2018 at 12:45:31PM +0100, Chris Wilson wrote: > > Quoting Imre Deak (2018-08-28 12:40:43) > > > During power domains initialization we acquire power well references for > > > power wells in the INIT power domain. The rest of power wells - which > > > BIOS could have left enabled - we can only acquire references as needed > > > during display HW readout. Thus during initialization these latter power > > > wells can have a refcount of 0 while still being enabled. To avoid the > > > false-positive state mismatch error this causes remove the check from > > > intel_power_domains_init_hw() and rely on the state check in > > > intel_power_domains_enable() which follows the HW readout. > > > > Missing from above is a quick explanation of how those extraneous > > powerwells are sanitizied. If we don't do the HW readout > > (i915.disable_display?) do we not then leave the powerwell active and so > > complain in a later verify_state()? > > These power wells (AUX and DDI on ICL) can only be enabled/disabled at > a specific spot in the modeset sequence, otherwise the power well > enable / disable operation will time out. That's the reason they're not > part of the INIT domain. For these we will acquire the references during > HW readout when noticing that the corresponding display HW block is active > and drop them when disabling these HW blocks (normally or as part of > display state sanitizatoionin). That way we'll ensure the proper spot > mentioned above for power well enabling/disabling. And that's also the reason why display HW readout had to be added back for i915.disable_display . --Imre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
