---
drivers/gpu/drm/i915/intel_lrc.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3f90c74038ef..fff2fbb6bac5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -161,7 +161,7 @@
/* Typical size of the average request (2 pipecontrols and a MI_BB) */
#define EXECLISTS_REQUEST_SIZE 64 /* bytes */
-#define WA_TAIL_DWORDS 2
+#define WA_TAIL_DWORDS 0
#define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
@@ -2195,8 +2195,10 @@ static int gen8_emit_flush_render(struct i915_request *request,
static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
{
/* Ensure there's always at least one preemption point per-request. */
- *cs++ = MI_ARB_CHECK;
- *cs++ = MI_NOOP;
+ if (WA_TAIL_DWORDS) {
+ *cs++ = MI_ARB_CHECK;
+ *cs++ = MI_NOOP;
+ }
request->wa_tail = intel_ring_offset(request, cs);
}
--
2.18.0
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