== Series Details == Series: Per context dynamic (sub)slice power-gating URL : https://patchwork.freedesktop.org/series/48194/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6a364f5371a6 drm/i915: Program RPCS for Broadwell f2e29d92ffdf drm/i915: Record the sseu configuration per-context & engine 5802b42315f5 drm/i915/perf: simplify configure all context function e3d46c7d1eb6 drm/i915/perf: reuse intel_lrc ctx regs macro 19449778b5b3 drm/i915/perf: lock powergating configuration to default when active 128663cebf31 drm/i915: Add global barrier support 46adb8a4a966 drm/i915: Explicitly mark Global GTT address spaces -:44: WARNING:BOOL_BITFIELD: Avoid using bool as bitfield. Prefer bool bitfields as unsigned int or u<8|16|32> #44: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:335: + bool is_ggtt:1; total: 0 errors, 1 warnings, 0 checks, 25 lines checked 491e75be6bef drm/i915: Expose RPCS (SSEU) configuration to userspace -:40: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #40: v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel) total: 0 errors, 1 warnings, 0 checks, 340 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
