POWER_DOMAIN_INIT is used when doing driver initialization or cleanup because driver will touch a lot of registers and using POWER_DOMAIN_INIT as a shortcut to power on or down every power well. So here skiping the call to the functions that actually power on or down power wells when domain is POWER_DOMAIN_INIT and display is disabled but it still grabs and releases the runtime pm reference to guarantee that hardware will be powered during initialization. This patch plus the changes in the previous patches is enough to not enable any power well when display is disabled, the only exception is POWER_DOMAIN_GT_IRQ that is used by gem to inhibits DC power savings while using GT. Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_drv.c | 8 +++++++- drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 743b03d50abb..5227cf0683f0 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1415,7 +1415,13 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) /* intel_power_domains_init_hw() counter part */ intel_display_set_init_power(dev_priv, false); - intel_power_domains_verify_state(dev_priv); + /* FIXME: When display is disabled all the power wells enabled by + * BIOS/firmware will still be enabled at this point so skip the + * verify state for now, this will be fixed in future patch disabling + * all the power wells that BIOS/firmware enabled. + */ + if (INTEL_INFO(dev_priv)->num_pipes) + intel_power_domains_verify_state(dev_priv); i915_driver_register(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8a84c77a1a88..7f0c10ee475a 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1543,6 +1543,9 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv, struct i915_power_domains *power_domains = &dev_priv->power_domains; struct i915_power_well *power_well; + WARN_ON(!INTEL_INFO(dev_priv)->num_pipes && + domain != POWER_DOMAIN_GT_IRQ); + for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) intel_power_well_get(dev_priv, power_well); @@ -1568,6 +1571,9 @@ void intel_display_power_get(struct drm_i915_private *dev_priv, intel_runtime_pm_get(dev_priv); + if (domain == POWER_DOMAIN_INIT && !INTEL_INFO(dev_priv)->num_pipes) + return; + mutex_lock(&power_domains->lock); __intel_display_power_get_domain(dev_priv, domain); @@ -1628,6 +1634,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, struct i915_power_domains *power_domains; struct i915_power_well *power_well; + if (domain == POWER_DOMAIN_INIT && !INTEL_INFO(dev_priv)->num_pipes) + goto end; + power_domains = &dev_priv->power_domains; mutex_lock(&power_domains->lock); @@ -1642,6 +1651,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); +end: intel_runtime_pm_put(dev_priv); } -- 2.18.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
