When DSI is operating in command mode, timing information
is given by the panel using TE signal. TE signals are received
as an interrupt. This patch adds the handler for TE interrupts.
Signed-off-by: Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_irq.c | 43 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a24c670..8ca2396 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1861,6 +1861,45 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
intel_guc_to_host_event_handler(&dev_priv->guc);
}
+void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
+ u32 iir_value)
+{
+ enum pipe pipe = INVALID_PIPE;
+ enum port port;
+ enum transcoder tc;
+ u32 val;
+
+ port = (iir_value & ICL_DSI0_TE) ? PORT_A : PORT_B;
+ tc = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
+
+ /* Check if DSI configured in command mode */
+ val = I915_READ(DSI_TRANS_FUNC_CONF(tc));
+ val = (val & OP_MODE_MASK) >> 28;
+
+ if (val != CMD_MODE_TE_GATE) {
+ DRM_ERROR("DSI trancoder not configured in command mode\n");
+ return;
+ }
+
+ /* Get PIPE for handling VBLANK event */
+ val = I915_READ(TRANS_DDI_FUNC_CTL(tc));
+ switch (val & TRANS_DDI_EDP_INPUT_MASK) {
+ case TRANS_DDI_EDP_INPUT_A_ON:
+ pipe = PIPE_A;
+ break;
+ case TRANS_DDI_EDP_INPUT_B_ONOFF:
+ pipe = PIPE_B;
+ break;
+ case TRANS_DDI_EDP_INPUT_C_ONOFF:
+ pipe = PIPE_C;
+ break;
+ default:
+ DRM_ERROR("Invalid PIPE\n");
+ }
+
+ drm_handle_vblank(&dev_priv->drm, pipe);
+}
+
static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
{
enum pipe pipe;
@@ -2815,6 +2854,10 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
found = true;
}
+ if (IS_ICELAKE(dev_priv) &&
+ (iir & (ICL_DSI0_TE | ICL_DSI1_TE)))
+ gen11_dsi_te_interrupt_handler(dev_priv, iir);
+
if (!found)
DRM_ERROR("Unexpected DE Port interrupt\n");
}
--
2.7.4
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