Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > Quoting Mika Kuoppala (2018-08-08 09:35:51) >> Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: >> >> > An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably >> > Valleyview) in that for the period following the GPU restart after a >> > reset, there are no GT interrupts received. From Ville's notes, bit 0 in >> > the HWSTAM corresponds to the render interrupt, and if we unmask it we >> > do see immediate resumption of GT interrupt delivery (via the master irq >> > handler) after the reset. >> > >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500 >> > Fixes: c5498089463b ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode") >> > References: d420a50c21ef ("drm/i915: Clean up the HWSTAM mess") >> > Testcase: igt/gem_eio/reset-stress >> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> >> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> > --- >> > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c >> > index 8003cef767ba..9b526b0f755a 100644 >> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c >> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c >> > @@ -388,7 +388,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) >> > } >> > >> > if (INTEL_GEN(dev_priv) >= 6) >> > - I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); >> > + I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xfffffffe); >> >> Yeah bit 0 is MI_USER_INTERRUPT on render. And execlists keeps all masked. >> >> There are bits for other engines too so add more paranoia? > > It's per ring though? It is, I was reading on wrong era (ilk). And found a table where the hardware status write isr change bits are and bit0 is an user interrupt. This is so unexpected that please add a comment to the code also that this is for after reset interrupt delivery weirdness. Acked-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
