From: "Srivatsa, Anusha" <anusha.srivatsa@xxxxxxxxx>
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
If FEC support exists, write to the FEC_READY bit
in the FEC_CONFIGURATION DPCD register.
v2: Mention External DP where ever FEC is mentioned
in the code.Check return status of dpcd reads. (Gaurav)
- Do regular mode check even if FEC is not supported. (manasi)
v3: Do not perform any dpcd writes in the atomic
check phase. (DK, Manasi)
v4: Use debug level logging for scenario where sink does
not support a feature. (DK)
Cc: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1a8329c..cb8b63e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -652,7 +652,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc_max_output_bpp = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
dsc_slice_count = drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
true);
- } else {
+ } else if (drm_dp_sink_supports_fec(&intel_dp->aux)) {
dsc_max_output_bpp = intel_dp_dsc_get_output_bpp(max_link_clock,
max_lanes,
target_clock,
@@ -660,7 +660,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp,
target_clock,
mode->hdisplay);
- }
+ } else
+ DRM_DEBUG_KMS("Sink device does not Support FEC\n");
}
if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
@@ -2000,6 +2001,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp))
return false;
+ /* DSC not supported if external DP sink does not support FEC */
+ if (!intel_dp_is_edp(intel_dp) &&
+ !drm_dp_sink_supports_fec(&intel_dp->aux)) {
+ DRM_DEBUG_KMS("Sink does not support Forward Error Correction, disabling Display Compression\n");
+ return false;
+ }
+
/* DSC not supported for DSC sink BPC < 8 */
if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) {
DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
--
2.7.4
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