Quoting Huang Rui (2018-08-07 11:56:24) > On Tue, Aug 07, 2018 at 11:45:00AM +0100, Chris Wilson wrote: > > amdgpu only uses shared-fences internally, but dmabuf importers rely on > > implicit write hazard tracking via the reservation_object.fence_excl. > > For example, the importer use the write hazard for timing a page flip to > > only occur after the exporter has finished flushing its write into the > > surface. As such, on exporting a dmabuf, we must either flush all > > outstanding fences (for we do not know which are writes and should have > > been exclusive) or alternatively create a new exclusive fence that is > > the composite of all the existing shared fences, and so will only be > > signaled when all earlier fences are signaled (ensuring that we can not > > be signaled before the completion of any earlier write). > > > > Testcase: igt/amd_prime/amd-to-i915 > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Alex Deucher <alexander.deucher@xxxxxxx> > > Cc: "Christian König" <christian.koenig@xxxxxxx> > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 70 ++++++++++++++++++++--- > > 1 file changed, 62 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c > > index 1c5d97f4b4dd..47e6ec5510b6 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c > > @@ -37,6 +37,7 @@ > > #include "amdgpu_display.h" > > #include <drm/amdgpu_drm.h> > > #include <linux/dma-buf.h> > > +#include <linux/dma-fence-array.h> > > > > static const struct dma_buf_ops amdgpu_dmabuf_ops; > > > > @@ -188,6 +189,57 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, > > return ERR_PTR(ret); > > } > > > > +static int > > +__reservation_object_make_exclusive(struct reservation_object *obj) > > +{ > > Why not you move the helper to reservation.c, and then export symbol for > this file? I have not seen anything else that would wish to use this helper. The first task is to solve this issue here before worrying about generalisation. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx