Quoting Michal Wajdeczko (2018-07-27 13:03:14) > On Fri, 27 Jul 2018 12:29:15 +0200, Chris Wilson > <chris@xxxxxxxxxxxxxxxxxx> wrote: > > > Quoting Jakub Bartmiński (2018-07-27 09:53:47) > >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > >> b/drivers/gpu/drm/i915/i915_gem_gtt.c > >> index d0acef299b9c..8ac5214b3648 100644 > >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > >> @@ -2917,6 +2917,14 @@ int i915_gem_init_ggtt(struct drm_i915_private > >> *dev_priv) > >> struct drm_mm_node *entry; > >> int ret; > >> > >> + /* > >> + * GuC requires the ring to be placed in Non-WOPCM memory. If > >> GuC is not > >> + * present or not in use we still need a small bias as ring > >> wraparound > >> + * at offset 0 sometimes hangs. No idea why. > >> + */ > >> + ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE, > >> + > >> intel_guc_wopcm_region_size(&dev_priv->guc)); > > > > Hmm, it feels like this should fit in with ggtt_init_hw, but the current > > setup makes that impossible. > > > > intel_guc_wopcm_region_size() is a peculiar path to access > > dev_priv->wopcm. > > > > Do we not want something like intel_wopcm_lower_reserved_size()? > > Earlier I was suggesting intel_guc_get_ggtt_pin_bias() as we should not > care how bias this is related to wopcm - only GuC should know that. :) Here I only care that the reason we exclude anything from the GGTT is self-evident. intel_guc_reserved_gtt_size(); intel_wopcm_reserved_gtt_size(); make more sense to me as to why we would even have a ggtt->pin_bias = intel_X_reserved_gtt_size() here. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
