On Wed, 2018-07-25 at 17:12 -0700, Paulo Zanoni wrote:
> The new recommendation from the spec is to simply not set this bit
> anymore. Not setting the bit would prevent some hangs that our driver
> manages to avoid since commit c8af5274c3cb ("drm/i915: enable the
> pipe/transcoder/planes later on HSW+"), and the theoretical downside
> of not setting the bit doesn't seem realistic according to the HW
> team. Let's follow their recommendation.
>
> BSpec: 20233
> References: commit c8af5274c3cb ("drm/i915: enable the
> pipe/transcoder/planes later on HSW+")
> Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
Also another steps were removed from initialization too, the previous
step 4 and parts of step 3 but if we really need to remove it we can do
it another patch.
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6b5aa3b074ec..cf89141b2281 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3372,10 +3372,6 @@ static void icl_display_core_init(struct
> drm_i915_private *dev_priv,
>
> /* 7. Setup MBUS. */
> icl_mbus_init(dev_priv);
> -
> - /* 8. CHICKEN_DCPR_1 */
> - I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1)
> |
> - CNL_DDI_CLOCK_REG_ACCESS_ON);
> }
>
> static void icl_display_core_uninit(struct drm_i915_private
> *dev_priv)
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