On Mon, 2018-07-09 at 17:39 -0700, Tarun Vyas wrote:
> In commit "drm/i915: Wait for PSR exit before checking for vblank
> evasion", the idea was to limit the PSR IDLE checks when PSR is
> actually supported. While CAN_PSR does do that check, it doesn't
> applies on a per-crtc basis. crtc_state->has_psr is a more granular
> check that only applies to pipe(s) that have PSR enabled.
>
> Currently, the driver supports PSR on port A + transcoder eDP, so
> only pipe A will wait for PSR to go IDLE, as it should, and other
> pipes should return immediately.
This still doesn't read right to me. Sorry for being pedantic,
documenting the hardware behaviour, especially when it comes to PSR is
important.
> Without the has_psr check, non-PSR pipe_updates (pipe B/C in this
> case), end up waiting on PSR pipe (pipe A in this case) to exit PSR,
> which may incur substantial delays for non-PSR pipe updates alongwith
> the fact the it doesn't makes any sense.
How about just saying "Without the crtc_state->has_psr check, we end up
waiting on the eDP transcoder's PSR_STATUS register irrespective of
whether the pipe being updated is driving it or not".
With the commit message altered, feel free to add
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
>
> Fixes: a608987970b9 ("drm/i915: Wait for PSR exit before checking for
> vblank evasion")
>
> v2: Remove unnecessary parantheses, make checkpatch happy.
>
> v3: Move the has_psr check to intel_psr_wait_for_idle and commit
> message changes (DK).
>
> v4: Derive dev_priv from intel_crtc_state (DK)
> Signed-off-by: Tarun Vyas <tarun.vyas@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 7 ++++++-
> drivers/gpu/drm/i915/intel_sprite.c | 2 +-
> 3 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 61e715ddd0d5..699073fbecb1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1923,7 +1923,7 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool
> debug);
> void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32
> psr_iir);
> void intel_psr_short_pulse(struct intel_dp *intel_dp);
> -int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv);
> +int intel_psr_wait_for_idle(const struct intel_crtc_state
> *new_crtc_state);
>
> /* intel_runtime_pm.c */
> int intel_power_domains_init(struct drm_i915_private *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 23acc9ac8d4d..e97db5dd75b1 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -717,11 +717,16 @@ void intel_psr_disable(struct intel_dp
> *intel_dp,
> cancel_work_sync(&dev_priv->psr.work);
> }
>
> -int intel_psr_wait_for_idle(struct drm_i915_private *dev_priv)
> +int intel_psr_wait_for_idle(const struct intel_crtc_state
> *new_crtc_state)
> {
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state-
> >base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> i915_reg_t reg;
> u32 mask;
>
> + if (!new_crtc_state->has_psr)
> + return 0;
> +
> /*
> * The sole user right now is intel_pipe_update_start(),
> * which won't race with psr_enable/disable, which is
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 4990d6e84ddf..9d6d1ac149da 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -118,7 +118,7 @@ void intel_pipe_update_start(const struct
> intel_crtc_state *new_crtc_state)
> * VBL interrupts will start the PSR exit and prevent a PSR
> * re-entry as well.
> */
> - if (CAN_PSR(dev_priv) && intel_psr_wait_for_idle(dev_priv))
> + if (intel_psr_wait_for_idle(new_crtc_state))
> DRM_ERROR("PSR idle timed out, atomic update may
> fail\n");
>
> local_irq_disable();
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