On Mon, 2018-07-09 at 12:24 -0700, Rodrigo Vivi wrote: > On Mon, Jul 09, 2018 at 11:30:00AM -0700, Dhinakaran Pandiyan wrote: > > > > On Sun, 2018-07-08 at 18:46 -0700, Tarun Vyas wrote: > > > > > > In commit "drm/i915: Wait for PSR exit before checking for vblank > > > evasion", the idea was to limit the PSR IDLE checks when PSR is > > > actually supported. While CAN_PSR does do that check, it doesn't > > > applies on a per-crtc basis. crtc_state->has_psr is a more > > > granular > > > check that avoids everything but pipe A, for the PSR IDLE check. > > > > > > With this, the PSR IDLE check should be a *no-op* for all but > > > pipe A > > > which is what was intended originally. > > > > > So, the problem is when we update a non-PSR pipe (B or C) and PSR > > is > > active on another pipe(A, specifically), we end up waiting for the > > pipe > > A MMIO to become idle. > > > > Can you please update the commit message as the commit message > > makes > > the per-pipe check sound like an optimization? > I truly doubt that multiple PSR pipes case doesn't work in our > driver. > if that works I'd assume it is by coincidence :P > > > > > This also points to a gap in our testing, I don't see a two pipe > > PSR > > related IGT. > The almost impossible mission here is to find any design with 2 eDP > connectors and both panels with PSR. > I meant, two pipes with PSR on one of them. I looked at the frontbuffer _tracking@psr subtests in https://intel-gfx-ci.01.org/tree/drm-tip/drmt ip.html, none of them were "2p". Ideally, a pipe update on a non-PSR pipe would have triggered this failure in CI. > > > > > > > > > > Fixes: a608987970b9 ("drm/i915: Wait for PSR exit before checking > > > for > > > vblank evasion") > > > > > > v2: Remove unnecessary parantheses, make checkpatch happy. > > > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > > > Signed-off-by: Tarun Vyas <tarun.vyas@xxxxxxxxx> > > > --- > > > drivers/gpu/drm/i915/intel_sprite.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c > > > b/drivers/gpu/drm/i915/intel_sprite.c > > > index 4990d6e84ddf..83880e3a5f3d 100644 > > > --- a/drivers/gpu/drm/i915/intel_sprite.c > > > +++ b/drivers/gpu/drm/i915/intel_sprite.c > > > @@ -118,7 +118,7 @@ void intel_pipe_update_start(const struct > > > intel_crtc_state *new_crtc_state) > > > * VBL interrupts will start the PSR exit and prevent a > > > PSR > > > * re-entry as well. > > > */ > > > - if (CAN_PSR(dev_priv) && > > > intel_psr_wait_for_idle(dev_priv)) > > > + if (new_crtc_state->has_psr && > > > intel_psr_wait_for_idle(dev_priv)) > > > DRM_ERROR("PSR idle timed out, atomic update may > > > fail\n"); > > > > > > local_irq_disable(); _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
