== Series Details == Series: ICELAKE DSI DRIVER (rev4) URL : https://patchwork.freedesktop.org/series/44823/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4441 -> Patchwork_9561 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44823/revisions/4/mbox/ == Known issues == Here are the changes found in Patchwork_9561 that come from known issues: === IGT changes === ==== Issues hit ==== igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) ==== Possible fixes ==== igt@gem_mmap_gtt@basic-copy: {fi-kbl-8809g}: DMESG-WARN -> PASS +7 {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 == Participating hosts (46 -> 42) == Additional (1): fi-cfl-8109u Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4441 -> Patchwork_9561 CI_DRM_4441: 3fe30c1d16d414ebf8c3ca95af28add100b7975e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4539: 8b3cc74c6911e9b2835fe6e160f84bae463a70ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9561: fb68c08ac6fa9e5975c8fb6b074db0ad65bde5d8 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == fb68c08ac6fa drm/i915/icl: Configure DSI transcoders 451da4606abd drm/i915/icl: Define TRANS_DSI_FUNC_CONF register fbbe21912b33 drm/i915/icl: Add macros for MMIO of DSI transcoder registers 186fc990ab12 drm/i915/icl: Get DSI transcoder for a given port acfb304958d7 drm/i915/icl: Program TA_TIMING_PARAM registers 359f3fc0e041 drm/i915/icl: Define TA_TIMING_PARAM registers e99851135d30 drm/i915/icl: Program DSI clock and data lane timing params 335d81a6a6a7 drm/i915/icl: Define data/clock lanes dphy timing registers 4fb266175e53 drm/i915/icl: Program T_INIT_MASTER registers 8d50beb06b68 drm/i915/icl: Define T_INIT_MASTER registers 09dbe3518361 drm/i915/icl: Enable DDI Buffer ec587a57f845 drm/i915/icl: DSI vswing programming sequence fb3fa3bd9904 drm/i915/icl: Configure lane sequencing of combo phy transmitter 2720e9beab3e drm/i915/icl: Define AUX lane registers for Port A/B 57a4e5d4fed4 drm/i915/icl: Power down unused DSI lanes 6a2070cfd165 drm/i915/icl: Define PORT_CL_DW_10 register c0cbc5197ef7 drm/i915/icl: Enable DSI IO power 0e3b3742fef0 drm/i915/icl: Define DSI mode ctl register 5b564741c1ea drm/i915/icl: Program DSI Escape clock Divider == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9561/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
