== Series Details == Series: ICELAKE DSI DRIVER (rev3) URL : https://patchwork.freedesktop.org/series/44823/ State : warning == Summary == $ dim checkpatch origin/drm-tip 232e4a2d6a15 drm/i915/icl: Define register for DSI PLL d3c59eb33fa4 drm/i915/icl: Program DSI Escape clock Divider -:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #28: new file mode 100644 -:33: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #33: FILE: drivers/gpu/drm/i915/gen11_dsi.c:1: +/* -:78: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #78: FILE: drivers/gpu/drm/i915/gen11_dsi.c:46: + I915_WRITE(ICL_DSI_ESC_CLK_DIV(port), + esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); -:84: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #84: FILE: drivers/gpu/drm/i915/gen11_dsi.c:52: + I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port), + esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); -:91: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #91: FILE: drivers/gpu/drm/i915/gen11_dsi.c:59: +gen11_dsi_pre_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config, total: 0 errors, 2 warnings, 3 checks, 78 lines checked a958e5547518 drm/i915/icl: Define DSI mode ctl register 2a7cad95c84a drm/i915/icl: Enable DSI IO power f481e14c3ae3 drm/i915/icl: Define PORT_CL_DW_10 register e56e95213123 drm/i915/icl: Power down unused DSI lanes 6f7275ce61cf drm/i915/icl: Define AUX lane registers for Port A/B b49066be1b42 drm/i915/icl: Configure lane sequencing of combo phy transmitter 7a8587c98089 drm/i915/icl: DSI vswing programming sequence -:33: CHECK:BRACES: Blank lines aren't necessary after an open brace '{' #33: FILE: drivers/gpu/drm/i915/gen11_dsi.c:39: + for_each_dsi_port(port, intel_dsi->ports) { + total: 0 errors, 0 warnings, 1 checks, 132 lines checked 62a43c99fbac drm/i915/icl: Enable DDI Buffer aeb82703e447 drm/i915/icl: Define T_INIT_MASTER registers e3758da591c4 drm/i915/icl: Program T_INIT_MASTER registers 231b77006a87 drm/i915/icl: Define data/clock lanes dphy timing registers -:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #31: FILE: drivers/gpu/drm/i915/i915_reg.h:10089: +#define CLK_PREP_TIME(x) (x << 28) -:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #33: FILE: drivers/gpu/drm/i915/i915_reg.h:10091: +#define CLK_ZERO_TIME(x) (x << 20) -:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #35: FILE: drivers/gpu/drm/i915/i915_reg.h:10093: +#define CLK_PRE_TIME(x) (x << 16) -:37: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #37: FILE: drivers/gpu/drm/i915/i915_reg.h:10095: +#define CLK_POST_TIME(x) (x << 8) -:39: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #39: FILE: drivers/gpu/drm/i915/i915_reg.h:10097: +#define CLK_TRAIL_TIME(x) (x << 0) -:52: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #52: FILE: drivers/gpu/drm/i915/i915_reg.h:10110: +#define HS_PREP_TIME(x) (x << 24) -:54: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #54: FILE: drivers/gpu/drm/i915/i915_reg.h:10112: +#define HS_ZERO_TIME(x) (x << 16) -:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #56: FILE: drivers/gpu/drm/i915/i915_reg.h:10114: +#define HS_TRAIL_TIME(x) (x << 8) -:58: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #58: FILE: drivers/gpu/drm/i915/i915_reg.h:10116: +#define HS_EXIT_TIME(x) (x << 0) total: 0 errors, 0 warnings, 9 checks, 46 lines checked 8deca2701ef1 drm/i915/icl: Program DSI clock and data lane timing params -:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #80: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:631: + ths_prepare_ns = max(mipi_config->ths_prepare, + mipi_config->tclk_prepare); -:114: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #114: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:655: + clk_zero_cnt = DIV_ROUND_UP( -:128: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #128: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:669: + hs_zero_cnt = DIV_ROUND_UP( -:190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #190: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:727: + prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, + ui_num * mul); -:196: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #196: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:731: + DRM_DEBUG_KMS("prepare count too high %u\n", + prepare_cnt); -:201: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #201: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:736: + exit_zero_cnt = DIV_ROUND_UP( -:226: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #226: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:748: + if (exit_zero_cnt < (55 * ui_den / ui_num) && + (55 * ui_den) % ui_num) -:231: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #231: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:753: + DRM_DEBUG_KMS("exit zero count too high %u\n", + exit_zero_cnt); -:250: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #250: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:764: + DRM_DEBUG_KMS("clock zero count too high %u\n", + clk_zero_cnt); total: 0 errors, 0 warnings, 9 checks, 293 lines checked b2eb5797678e drm/i915/icl: Define TA_TIMING_PARAM registers -:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #31: FILE: drivers/gpu/drm/i915/i915_reg.h:10129: +#define TA_SURE_TIME(x) (x << 16) total: 0 errors, 0 warnings, 1 checks, 20 lines checked 8b049558aeab drm/i915/icl: Program TA_TIMING_PARAM registers 8d034248b3cc drm/i915/icl: Get DSI transcoder for a given port -:20: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #20: FILE: drivers/gpu/drm/i915/gen11_dsi.c:30: +static enum transcoder __attribute__((unused)) dsi_port_to_transcoder( total: 0 errors, 0 warnings, 1 checks, 27 lines checked 7177c61bab6c drm/i915/icl: Add macros for MMIO of DSI transcoder registers bf595a2d4a1d drm/i915/icl: Define TRANS_DSI_FUNC_CONF register -:26: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #26: FILE: drivers/gpu/drm/i915/i915_reg.h:10143: +#define OP_MODE(x) (x << 28) -:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #33: FILE: drivers/gpu/drm/i915/i915_reg.h:10150: +#define PIX_FMT(x) (x << 16) -:43: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #43: FILE: drivers/gpu/drm/i915/i915_reg.h:10160: +#define PIX_VIRT_CHAN(x) (x << 12) -:45: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #45: FILE: drivers/gpu/drm/i915/i915_reg.h:10162: +#define PIX_BUF_THRESHOLD(x) ((x & 0x3) << 10) -:51: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #51: FILE: drivers/gpu/drm/i915/i915_reg.h:10168: +#define CONTINUOUS_CLK(x) (x << 8) -:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #56: FILE: drivers/gpu/drm/i915/i915_reg.h:10173: +#define LINK_CALIBRATION(x) (x << 4) -:61: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues #61: FILE: drivers/gpu/drm/i915/i915_reg.h:10178: +#define S3D_ORIENTATION(x) (x << 1) total: 0 errors, 0 warnings, 7 checks, 53 lines checked 10c6389e48e2 drm/i915/icl: Configure DSI transcoders -:54: CHECK:OPEN_ENDED_LINE: Lines should not end with a '(' #54: FILE: drivers/gpu/drm/i915/gen11_dsi.c:356: + tmp |= LINK_CALIBRATION( total: 0 errors, 0 warnings, 1 checks, 121 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
