> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, July 4, 2018 8:25 PM
> To: Chauhan, Madhav <madhav.chauhan@xxxxxxxxx>; intel-
> gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx>; Zanoni, Paulo R
> <paulo.r.zanoni@xxxxxxxxx>; Shankar, Uma <uma.shankar@xxxxxxxxx>;
> Chauhan, Madhav <madhav.chauhan@xxxxxxxxx>
> Subject: Re: [PATCH v2 07/20] drm/i915/icl: Define AUX lane registers for Port
> A/B
>
> On Tue, 03 Jul 2018, Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
> wrote:
> > This patch defines AUX lane registers for PORT_PCS_DW1, PORT_TX_DW2,
> > PORT_TX_DW4, PORT_TX_DW5 used during dsi enabling.
> >
> > Signed-off-by: Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 3fa8f02..d3ce1a9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1780,16 +1780,21 @@ enum i915_power_well_id {
> >
> _CNL_PORT_PCS_DW1_LN0_D, \
> >
> _CNL_PORT_PCS_DW1_LN0_AE, \
> >
> _CNL_PORT_PCS_DW1_LN0_F))
> > +
> > #define _ICL_PORT_PCS_DW1_GRP_A 0x162604
> > #define _ICL_PORT_PCS_DW1_GRP_B 0x6C604
> > #define _ICL_PORT_PCS_DW1_LN0_A 0x162804
> > #define _ICL_PORT_PCS_DW1_LN0_B 0x6C804
> > +#define _ICL_PORT_PCS_DW1_AUX_B 0x6c304
> > #define ICL_PORT_PCS_DW1_GRP(port) _MMIO_PORT(port,\
> >
> _ICL_PORT_PCS_DW1_GRP_A, \
> >
> _ICL_PORT_PCS_DW1_GRP_B)
> > #define ICL_PORT_PCS_DW1_LN0(port) _MMIO_PORT(port, \
> >
> _ICL_PORT_PCS_DW1_LN0_A, \
> >
> _ICL_PORT_PCS_DW1_LN0_B)
> > +#define ICL_PORT_PCS_DW1_AUX(port) _MMIO_PORT(port, \
> > +
> _CNL_PORT_PCS_DW1_GRP_AE, \
>
> I think for consistency with the rest of the registers here you should add
> 0x162304 as _ICL_PORT_PCS_DW1_AUX_A. Clearly that's been decided for
> the rest of these registers.
>
> > +
> _ICL_PORT_PCS_DW1_AUX_B)
> > #define COMMON_KEEPER_EN (1 << 26)
> >
> > /* CNL Port TX registers */
> > @@ -1826,16 +1831,23 @@ enum i915_power_well_id {
> > #define _ICL_PORT_TX_DW2_GRP_B 0x6C688
> > #define _ICL_PORT_TX_DW2_LN0_A 0x162888
> > #define _ICL_PORT_TX_DW2_LN0_B 0x6C888
> > +#define _ICL_PORT_TX_DW2_AUX_A 0x162388
> > +#define _ICL_PORT_TX_DW2_AUX_B 0x6c388
> > #define ICL_PORT_TX_DW2_GRP(port) _MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW2_GRP_A, \
> >
> _ICL_PORT_TX_DW2_GRP_B)
> > #define ICL_PORT_TX_DW2_LN0(port) _MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW2_LN0_A, \
> >
> _ICL_PORT_TX_DW2_LN0_B)
> > +#define ICL_PORT_TX_DW2_AUX(port) _MMIO_PORT(port, \
> > +
> _ICL_PORT_TX_DW2_AUX_A, \
> > +
> _ICL_PORT_TX_DW2_AUX_B)
> > #define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
> > #define SWING_SEL_UPPER_MASK (1 << 15)
> > #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
> > #define SWING_SEL_LOWER_MASK (0x7 << 11)
> > +#define FRC_LATENCY_OPTIM_MASK (0x7 << 8)
> > +#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8)
> ^^^
>
> Three spaces like the rest of them.
>
> With the above two things fixed,
>
> Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Ok. Thanks!!
Regards,
Madhav
>
>
> > #define RCOMP_SCALAR(x) ((x) << 0)
> > #define RCOMP_SCALAR_MASK (0xFF << 0)
> >
> > @@ -1851,6 +1863,8 @@ enum i915_power_well_id {
> > #define _ICL_PORT_TX_DW4_LN0_A 0x162890
> > #define _ICL_PORT_TX_DW4_LN1_A 0x162990
> > #define _ICL_PORT_TX_DW4_LN0_B 0x6C890
> > +#define _ICL_PORT_TX_DW4_AUX_A 0x162390
> > +#define _ICL_PORT_TX_DW4_AUX_B 0x6c390
> > #define ICL_PORT_TX_DW4_GRP(port) _MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW4_GRP_A, \
> >
> _ICL_PORT_TX_DW4_GRP_B)
> > @@ -1859,6 +1873,9 @@ enum i915_power_well_id {
> >
> _ICL_PORT_TX_DW4_LN0_B) + \
> > ((ln) *
> (_ICL_PORT_TX_DW4_LN1_A - \
> >
> _ICL_PORT_TX_DW4_LN0_A)))
> > +#define ICL_PORT_TX_DW4_AUX(port) _MMIO_PORT(port, \
> > +
> _ICL_PORT_TX_DW4_AUX_A, \
> > +
> _ICL_PORT_TX_DW4_AUX_B)
> > #define LOADGEN_SELECT (1 << 31)
> > #define POST_CURSOR_1(x) ((x) << 12)
> > #define POST_CURSOR_1_MASK (0x3F << 12)
> > @@ -1873,12 +1890,17 @@ enum i915_power_well_id {
> > #define _ICL_PORT_TX_DW5_GRP_B 0x6C694
> > #define _ICL_PORT_TX_DW5_LN0_A 0x162894
> > #define _ICL_PORT_TX_DW5_LN0_B 0x6C894
> > +#define _ICL_PORT_TX_DW5_AUX_A 0x162394
> > +#define _ICL_PORT_TX_DW5_AUX_B 0x6c394
> > #define ICL_PORT_TX_DW5_GRP(port) _MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW5_GRP_A, \
> >
> _ICL_PORT_TX_DW5_GRP_B)
> > #define ICL_PORT_TX_DW5_LN0(port) _MMIO_PORT(port, \
> >
> _ICL_PORT_TX_DW5_LN0_A, \
> >
> _ICL_PORT_TX_DW5_LN0_B)
> > +#define ICL_PORT_TX_DW5_AUX(port) _MMIO_PORT(port, \
> > +
> _ICL_PORT_TX_DW5_AUX_A, \
> > +
> _ICL_PORT_TX_DW5_AUX_B)
> > #define TX_TRAINING_EN (1 << 31)
> > #define TAP2_DISABLE (1 << 30)
> > #define TAP3_DISABLE (1 << 29)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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