On Mon, Dec 10, 2012 at 9:36 AM, Daniel Vetter <daniel at ffwll.ch> wrote: >> >> + tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK); >> >> + tmp |= SBI_DBUFF0_ENABLE; >> >> + intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK); >> > >> > Th ULT path is missing there. >> >> The ULT will never reach this point, there's not VGA. > > Added a comment. To go to the bottom of this, I wanted to understand why you can enable the PCH SSC. It is recommended to use the internal SSC source on ULT platforms. The PCH SSC source is then only used for clock bending. Fortunately the PLL Select bits in SPLL_CTL paper over this difference between the internal and PCH SSC sources, selecting the right one based on a fused bit. And Paulo does check if we have VGA at the start, so indeed, all is good (I believe)! -- Damien
