On Sat, Dec 1, 2012 at 2:04 PM, Paulo Zanoni <przanoni at gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> We need this code to init the PCH SSC refclk and the FDI registers.
> The BIOS does this too and that's why VGA worked before this patch,
> until you tried to suspend the machine...
>
> This patch implements the "Sequence to enable CLKOUT_DP for FDI usage
> and configure PCH FDI/IO" from our documentation.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> + if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
> + is_sdv = true;
Maybe have a IS_SDV() or IS_HSW_SDV() macro like we have a IS_ULT()
one? The check should be on the PCH revision but hopefully there's a
1:1 correlation?
> + if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
> + FDI_MPHY_IOSFSB_RESET_STATUS, 100))
> + DRM_ERROR("FDI mPHY resert assert timeout\n");
s/resert/reset/
> +
> + tmp = I915_READ(SOUTH_CHICKEN2);
> + tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
> + I915_WRITE(SOUTH_CHICKEN2, tmp);
> +
> + if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
> + FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
> + 100))
> + DRM_ERROR("FDI mPHY reset de-assert timeout\n");
> + }
When either of those two waits error out, we carry on the sequence. We
should probably fail and disable the VGA output (one of those error
paths that never get to be tested, yey! I don't know how well we
support connectors disappearing)?
> + tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
> + tmp |= SBI_DBUFF0_ENABLE;
> + intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
Th ULT path is missing there.
I double checked the programming, looks good. I'll follow up with an
amended patch for the 2 first bikesheds, leave the error path alone,
and add the ULT path as a separate patch.
--
Damien
