Quoting Tvrtko Ursulin (2018-06-28 13:15:07) > > On 28/06/2018 12:59, Chris Wilson wrote: > > On HW reset, the HW clears the write pointer (to 0). But since it also > > writes its first CSB entry to slot 0, we need to reset the write pointer > > back to the element before (so the first entry we read is 0). > > > > This is required for the next patch, where we trust the CSB completely! > > > > v2: Use _MASKED_FIELD > > v3: Store the reset value, so that we differentiate between mmio/hwsp > > transparently and without pretense. > > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/intel_lrc.c | 23 +++++++++++++++++++++-- > > drivers/gpu/drm/i915/intel_ringbuffer.h | 9 +++++++++ > > 2 files changed, 30 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > > index 8531a5b6f6ff..49bf5048043c 100644 > > --- a/drivers/gpu/drm/i915/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/intel_lrc.c > > @@ -884,6 +884,21 @@ static void reset_irq(struct intel_engine_cs *engine) > > clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); > > } > > > > +static void reset_csb_pointers(struct intel_engine_execlists *execlists) > > +{ > > + /* > > + * After a reset, the HW starts writing into CSB entry [0]. We > > + * therefore have to set our HEAD pointer back one entry so that > > + * the *first* entry we check is entry 0. To complicate this further, > > + * as we don't wait for the first interrupt after reset, we have to > > + * fake the HW write to point back to the last entry so that our > > + * inline comparison of our cached head position against the last HW > > + * write works even before the first interrupt. > > + */ > > + execlists->csb_head = execlists->csb_write_reset & 0xff; > > Idea for avoiding the & 0xff and applying the trick throughout - make > csb_head u8. :) Just leaves intel_engine_execlists full of holes. It did close my mind. They may just spontaneously rearrange themselves... -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx