> -----Original Message----- > From: Chauhan, Madhav > Sent: Friday, June 15, 2018 3:51 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; Zanoni, Paulo R > <paulo.r.zanoni@xxxxxxxxx>; Shankar, Uma <uma.shankar@xxxxxxxxx>; Vivi, > Rodrigo <rodrigo.vivi@xxxxxxxxx>; Chauhan, Madhav > <madhav.chauhan@xxxxxxxxx> > Subject: [PATCH 00/20] ICELAKE DSI DRIVER > > From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to > GPU/Display Engine and same could be extended for future Intel platforms > as well. > DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification. > > So, a new DSI driver has been added inside I915. > > Given below patches are the part of new DSI driver which implements BSPEC > sequence till transcoder configuration. Rest of the patches (~45) will be > published to GITHUB by mid next week and will share the GITHUB link here > so that complete implementation can be looked at by reviewers. Published remaining changes of v1 to GITHUB. Tree can be downloaded using: git clone https://github.com/madhavchauhan/Intel-DSI-Driver.git Regards, Madhav > > Madhav Chauhan (20): > drm/i915/icl: Define register for DSI PLL > drm/i915/icl: Program DSI Escape clock Divider > drm/i915/icl: Define DSI mode ctl register > drm/i915/icl: Enable DSI IO power > drm/i915/icl: Define PORT_CL_DW_10 register > drm/i915/icl: Power down unused DSI lanes > drm/i915/icl: Define AUX lane registers for Port A/B > drm/i915/icl: Configure lane sequencing of combo phy transmitter > drm/i915/icl: DSI vswing programming sequence > drm/i915/icl: Enable DDI Buffer > drm/i915/icl: Define T_INIT_MASTER registers > drm/i915/icl: Program T_INIT_MASTER registers > drm/i915/icl: Define data/clock lanes dphy timing registers > drm/i915/icl: Program DSI clock and data lane timing params > drm/i915/icl: Define TA_TIMING_PARAM registers > drm/i915/icl: Program TA_TIMING_PARAM registers > drm/i915/icl: Get DSI transcoder for a given port > drm/i915/icl: Add macros for MMIO of DSI transcoder registers > drm/i915/icl: Define TRANS_DSI_FUNC_CONF register > drm/i915/icl: Configure DSI transcoders > > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/i915_reg.h | 174 ++++++++++++++ > drivers/gpu/drm/i915/intel_display.h | 6 +- > drivers/gpu/drm/i915/intel_dsi.h | 7 + > drivers/gpu/drm/i915/intel_dsi_new.c | 455 > +++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_dsi_vbt.c | 202 +++++++++++----- > 6 files changed, 787 insertions(+), 58 deletions(-) create mode 100644 > drivers/gpu/drm/i915/intel_dsi_new.c > > -- > 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
