As we want to compare a templated tiling pattern against the target_bo, we need to know that the swizzling is compatible. Or else the two tiling pattern may differ due to underlying page address that we cannot know, and so the test may sporadically fail. References: https://bugs.freedesktop.org/show_bug.cgi?id=102575 Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> --- tests/gem_tiled_partial_pwrite_pread.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c index fe573c37c..83c57c07d 100644 --- a/tests/gem_tiled_partial_pwrite_pread.c +++ b/tests/gem_tiled_partial_pwrite_pread.c @@ -249,6 +249,24 @@ static void test_partial_read_writes(void) } } +static bool known_swizzling(uint32_t handle) +{ + struct drm_i915_gem_get_tiling2 { + uint32_t handle; + uint32_t tiling_mode; + uint32_t swizzle_mode; + uint32_t phys_swizzle_mode; + } arg = { + .handle = handle, + }; +#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2) + + if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg)) + return false; + + return arg.phys_swizzle_mode == arg.swizzle_mode; +} + igt_main { uint32_t tiling_mode = I915_TILING_X; @@ -271,6 +289,12 @@ igt_main &tiling_mode, &scratch_pitch, 0); igt_assert(tiling_mode == I915_TILING_X); igt_assert(scratch_pitch == 4096); + + /* + * As we want to compare our template tiled pattern against + * the target bo, we need consistent swizzling on both. + */ + igt_require(known_swizzling(scratch_bo->handle)); staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096); tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024, BO_SIZE/4096, 4, -- 2.18.0.rc2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
