> -----Original Message-----
> From: Zanoni, Paulo R
> Sent: Friday, June 15, 2018 11:41 PM
> To: Chauhan, Madhav <madhav.chauhan@xxxxxxxxx>; intel-
> gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; Shankar, Uma
> <uma.shankar@xxxxxxxxx>; Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx>
> Subject: Re: [PATCH 02/20] drm/i915/icl: Program DSI Escape clock Divider
>
> Em Sex, 2018-06-15 às 23:30 +0530, Chauhan, Madhav escreveu:
> > > -----Original Message-----
> > > From: Zanoni, Paulo R
> > > Sent: Friday, June 15, 2018 11:00 PM
> > > To: Chauhan, Madhav <madhav.chauhan@xxxxxxxxx>; intel-
> > > gfx@xxxxxxxxxxxxxxxxxxxxx
> > > Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; Shankar, Uma
> > > <uma.shankar@xxxxxxxxx>; Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx>
> > > Subject: Re: [PATCH 02/20] drm/i915/icl: Program DSI Escape clock
> > > Divider
> > >
> > > Em Sex, 2018-06-15 às 15:51 +0530, Madhav Chauhan escreveu:
> > > > Escape Clock is used for LP communication across the DSI Link. To
> > > > achieve the constant frequency of the escape clock from the
> > > > variable DPLL frequency output, a variable divider(M) is needed.
> > > > This patch programs the same.
> > > >
> > > > Signed-off-by: Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
> > > > ---
> > > > drivers/gpu/drm/i915/Makefile | 1 +
> > > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > > drivers/gpu/drm/i915/intel_dsi_new.c | 65
> > > > ++++++++++++++++++++++++++++++++++++
> > > > 3 files changed, 67 insertions(+) create mode 100644
> > > > drivers/gpu/drm/i915/intel_dsi_new.c
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/Makefile
> > > > b/drivers/gpu/drm/i915/Makefile index 4c6adae..a5f60c8 100644
> > > > --- a/drivers/gpu/drm/i915/Makefile
> > > > +++ b/drivers/gpu/drm/i915/Makefile
> > > > @@ -142,6 +142,7 @@ i915-y += dvo_ch7017.o \
> > > > intel_dp_mst.o \
> > > > intel_dp.o \
> > > > intel_dsi.o \
> > > > + intel_dsi_new.o \
> > > > intel_dsi_dcs_backlight.o \
> > > > intel_dsi_pll.o \
> > > > intel_dsi_vbt.o \
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h index bf2d3e4..55ef57d 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -9350,6 +9350,7 @@ enum skl_power_gate {
> > > > _ICL_DPHY_ESC_CL
> > > > K_DI
> > > > V0, \
> > > > _ICL_DPHY_ESC_CL
> > > > K_DI
> > > > V1)
> > > > #define ICL_ESC_CLK_DIV_MASK 0x1ff
> > > > +#define DSI_MAX_ESC_CLK 20000
> > > > /* in KHz */
> > > >
> > > > /* Gen4+ Timestamp and Pipe Frame time stamp registers */
> > > > #define GEN4_TIMESTAMP _MMIO(0x2358)
> > > > diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
> > > > b/drivers/gpu/drm/i915/intel_dsi_new.c
> > > > new file mode 100644
> > > > index 0000000..0d325ca
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/i915/intel_dsi_new.c
> > > > @@ -0,0 +1,65 @@
> > >
> > > I am not a lawyer nor a license expert, but as far as I understand
> > > (and I may be wrong):
> > >
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > >
> > > the line above...
> >
> > I was getting checkpatch warning and then I explored the options and
> > found this.
> > Looked at some of the recent files added (intel_hdcp.c) as well and
> > they have this option .
> >
> > >
> > > > +/*
> > > > + * Copyright © 2018 Intel Corporation
> > > > + *
> > > > + * Permission is hereby granted, free of charge, to any person
> > > > obtaining a
> > > > + * copy of this software and associated documentation files (the
> > > > "Software"),
> > > > + * to deal in the Software without restriction, including
> > > > without
> > > > limitation
> > > > + * the rights to use, copy, modify, merge, publish, distribute,
> > > > sublicense,
> > > > + * and/or sell copies of the Software, and to permit persons to
> > > > whom
> > > > the
> > > > + * Software is furnished to do so, subject to the following
> > > > conditions:
> > > > + *
> > > > + * The above copyright notice and this permission notice
> > > > (including
> > > > the next
> > > > + * paragraph) shall be included in all copies or substantial
> > > > portions of the
> > > > + * Software.
> > > > + *
> > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> > >
> > > KIND,
> > > > EXPRESS OR
> > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > > > MERCHANTABILITY,
> > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN
> NO
> > > > EVENT SHALL
> > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> > >
> > > DAMAGES
> > > > OR OTHER
> > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> > >
> > > OTHERWISE,
> > > > ARISING
> > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> USE
> > >
> > > OR
> > > > OTHER
> > > > + * DEALINGS IN THE SOFTWARE.
> > >
> > > ... does not seem to match the license above.
> >
> > Can you please be more specific here??
>
> Please read the two links I gave. The file has an SPDX identifier for GPL-2.0+
> but license text is the MIT license.
Thanks. I used this from intel_cdclk.c.
But what's the guideline here. Do we need to include SPDX id in new files,
If yes, what license to specify (I assume GPL 2.0)??
Any reference file in I915 where license text can be looked at??
Jani N/Rodrigo: Any suggestion??
Regards,
Madhav
>
> >
> > Regards,
> > Madhav
> >
> > >
> > > https://www.kernel.org/doc/html/latest/process/license-rules.html
> > >
> > > https://spdx.org/
> > >
> > > Thanks,
> > > Paulo
> > >
> > > > + *
> > > > + * Authors:
> > > > + * Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
> > > > + * Jani Nikula <jani.nikula@xxxxxxxxx>
> > > > + */
> > > > +
> > > > +#include "intel_dsi.h"
> > > > +
> > > > +static void gen11_dsi_program_esc_clk_div(struct intel_encoder
> > > > *encoder)
> > > > +{
> > > > + struct drm_i915_private *dev_priv = to_i915(encoder-
> > > > > base.dev);
> > > >
> > > > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder-
> > > > > base);
> > > >
> > > > + enum port port;
> > > > + u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> > > > > pixel_format);
> > > >
> > > > + u32 afe_clk_khz; /* 8X Clock */
> > > > + u32 esc_clk_div_m;
> > > > +
> > > > + afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
> > > > + intel_dsi->lane_count);
> > > > +
> > > > + esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz,
> > > > DSI_MAX_ESC_CLK);
> > > > +
> > > > + for_each_dsi_port(port, intel_dsi->ports) {
> > > > + I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
> > > > + esc_clk_div_m &
> > > > ICL_ESC_CLK_DIV_MASK);
> > > > + POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
> > > > + }
> > > > +
> > > > + for_each_dsi_port(port, intel_dsi->ports) {
> > > > + I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
> > > > + esc_clk_div_m &
> > > > ICL_ESC_CLK_DIV_MASK);
> > > > + POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
> > > > + }
> > > > +}
> > > > +
> > > > +static void __attribute__((unused)) gen11_dsi_pre_enable(
> > > > + struct intel_encoder *encoder,
> > > > + const struct intel_crtc_state
> > > > *pipe_config,
> > > > + const struct drm_connector_state
> > > > *conn_state)
> > > > +{
> > > > + /* step3: enable DSI PLL */
> > > > + gen11_dsi_program_esc_clk_div(encoder);
> > > > +}
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