Re: [PATCH] drm/i915: Enable provoking vertex fix on Gen9 systems.

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Quoting Chris Wilson (2018-06-15 22:06:05)
> From: Kenneth Graunke <kenneth@xxxxxxxxxxxxx>
> 
> The SF and clipper units mishandle the provoking vertex in some cases,
> which can cause misrendering with shaders that use flat shaded inputs.
> 
> There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN
> (for the clipper) that work around the issue.  These registers are
> unfortunately not part of the logical context (even the power context),
> and so we must reload them every time we start executing in a context.
> 
> Bugzilla: https://bugs.freedesktop.org/103047
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>

One note below.

> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1575,11 +1575,21 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
>         /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
>         batch = gen8_emit_flush_coherentl3_wa(engine, batch);
>  
> +       *batch++ = MI_LOAD_REGISTER_IMM(3);
> +
>         /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
> -       *batch++ = MI_LOAD_REGISTER_IMM(1);
>         *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
>         *batch++ = _MASKED_BIT_DISABLE(
>                         GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
> +
> +       /* BSpec: 11391 */
> +       *batch++ = i915_mmio_reg_offset(FF_SLICE_CHICKEN);
> +       *batch++ = _MASKED_BIT_ENABLE(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX);
> +
> +       /* BSpec: 11299 */
> +       *batch++ = i915_mmio_reg_offset(_3D_CHICKEN3);
> +       *batch++ = _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX);

I'm almost betting that somebody will take one of these 3 off without
noticing the distant LOAD_REGISTER_IMM(). To perfect this, const table
of pairs and use ARRAY_SIZE()? Then we're also one step closer to the
const W/A tables...

Regards, Joonas
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