On Thu, Jun 14, 2018 at 05:45:03PM -0700, Manasi Navare wrote:
> On Thu, Jun 14, 2018 at 12:24:32PM -0700, Rodrigo Vivi wrote:
> > On Fri, Jun 01, 2018 at 04:43:26PM -0700, Paulo Zanoni wrote:
> > > Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> > > > On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > > > > From: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> > > > >
> > > > > For ICL, on Combo PHY the allowed max rates are:
> > > > > - HBR3 8.1 eDP (DDIA)
> > > > > - HBR2 5.4 DisplayPort (DDIB)
> > > > > and for MG PHY/TC DDI Ports allowed DP rates are:
> > > > > - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> > > > > - DP on legacy connector - DDIC/D/E/F)
> > > > >
> > > > > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> > > > > Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> > > > > Cc: James Ausmus <james.ausmus@xxxxxxxxx>
> > > > > Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> > > > > Signed-off-by: James Ausmus <james.ausmus@xxxxxxxxx>
> > > >
> > > > Reviewed-by: James Ausmus <james.ausmus@xxxxxxxxx>
> > > >
> > > > > ---
> > > > > drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> > > > > 1 file changed, 19 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > > index 5109023abe28..3ee8e74cf2b8 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp
> > > > > *intel_dp)
> > > > > return 810000;
> > > > > }
> > > > >
> > > > > +static int icl_max_source_rate(struct intel_dp *intel_dp)
> > > > > +{
> > > > > + struct intel_digital_port *dig_port =
> > > > > dp_to_dig_port(intel_dp);
> > > > > + enum port port = dig_port->base.port;
> > > > > +
> > > > > + /* On Combo PHY port A max speed is HBR3 for all Vccio
> > > > > voltages
> > > > > + * and on Combo PHY Port B the maximum supported is HBR2.
> > > > > + */
> > > > > + if (port == PORT_B)
> > > > > + return 540000;
> > > > > +
> > > > > + return 810000;
> > > > > +}
> > > > > +
> > > > > static void
> > > > > intel_dp_set_source_rates(struct intel_dp *intel_dp)
> > > > > {
> > > > > @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp
> > > > > *intel_dp)
> > > > > /* This should only be done once */
> > > > > WARN_ON(intel_dp->source_rates || intel_dp-
> > > > > >num_source_rates);
> > > > >
> > > > > - if (IS_CANNONLAKE(dev_priv)) {
> > > > > + if (INTEL_GEN(dev_priv) >= 10) {
> > > > > source_rates = cnl_rates;
> > > > > size = ARRAY_SIZE(cnl_rates);
> > > > > - max_rate = cnl_max_source_rate(intel_dp);
> > > > > + if (IS_ICELAKE(dev_priv))
> > > > > + max_rate = icl_max_source_rate(intel_dp);
> > > > > + else
> > > > > + max_rate = cnl_max_source_rate(intel_dp);
> > >
> > > Bikeshed: changing this to "if (IS_CANNONLAKE())" would help ensuring
> > > any possible future platform would be using the ICL table instead of
> > > the CNL one.
> >
> > I agree... but I'd prefer s/IS_ICELAKE/gen >= 11
>
> Ok, so remove IS_CANNONLAKE and only have the code for Gen >=11 right?
> So remove the cnl_max_source_rate also?
No no, the rest of the patch is okay and should stay...
only instead of IS_ICELAKE you use gen >= 11
>
> Regards
> Manasi
>
> >
> > >
> > >
> > > > > } else if (IS_GEN9_LP(dev_priv)) {
> > > > > source_rates = bxt_rates;
> > > > > size = ARRAY_SIZE(bxt_rates);
> > > > > --
> > > > > 2.14.3
> > > > >
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