On Thu, Jun 14, 2018 at 01:34:33PM -0700, José Roberto de Souza wrote:
> Sink can be configured to calculate the CRC over the static frame and
> compare with the CRC calculated and transmited in the VSC SDP by
> source, if there is a mismatch sink will do a short pulse in HPD
> and set DP_PSR_LINK_CRC_ERROR in DP_PSR_ERROR_STATUS.
>
> Spec: 7723
>
> v4:
> patch moved to after 'drm/i915/psr: Avoid PSR exit max time timeout'
> to avoid touch in 2 patches EDP_PSR_DEBUG.
>
> v3:
> disabling PSR instead of exiting on error
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 16 ++++++++++++----
> 2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 140f6a27d696..ed34ccd81c7c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4038,6 +4038,7 @@ enum {
> #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
> #define EDP_PSR_TP1_TP2_SEL (0<<11)
> #define EDP_PSR_TP1_TP3_SEL (1<<11)
> +#define EDP_PSR_CRC_ENABLE (1<<10) /* BDW+ */
> #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
> #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
> #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 177cd57b1029..cf72b79caf3f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -360,6 +360,8 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>
> if (dev_priv->psr.link_standby)
> dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> + if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
> + dpcd_val |= DP_PSR_CRC_VERIFICATION;
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
>
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
> @@ -415,6 +417,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
> else
> val |= EDP_PSR_TP1_TP2_SEL;
>
> + if (INTEL_GEN(dev_priv) >= 8)
> + val |= EDP_PSR_CRC_ENABLE;
> +
> val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
> I915_WRITE(EDP_PSR_CTL, val);
> }
> @@ -1032,16 +1037,19 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> goto exit;
> }
>
> - if (val & DP_PSR_RFB_STORAGE_ERROR) {
> - DRM_DEBUG_KMS("PSR RFB storage error, exiting PSR\n");
> + if (val & (DP_PSR_RFB_STORAGE_ERROR | DP_PSR_LINK_CRC_ERROR)) {
> + if (val & DP_PSR_RFB_STORAGE_ERROR)
I believe we can avoid the duplication of the conditions here...
maybe with:
if (val & DP_PSR_RFB_STORAGE_ERROR)
//msg
else if (val & DP_PSR_LINK_CRC_ERROR)
//msg
else
goto clear
intel_psr_disable_locked()
> + DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
> + if (val & DP_PSR_LINK_CRC_ERROR)
> + DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n");
> psr_disable(intel_dp);
> }
> - if (val & (DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | DP_PSR_LINK_CRC_ERROR))
> + if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
> DRM_ERROR("PSR_ERROR_STATUS not handled %x\n", val);
clear:
> /* clear status register */
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
>
> - /* TODO: handle other PSR/PSR2 errors */
> + /* TODO: handle PSR2 errors */
> exit:
> mutex_unlock(&psr->lock);
> }
> --
> 2.17.1
>
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