This is a note to let you know that I've just added the patch titled
x86/cpufeature: Remove cpu_has_clflush
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
x86-cpufeature-remove-cpu_has_clflush.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 906bf7fda2c9cf5c1762ec607943ed54b6c5b203 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp@xxxxxxx>
Date: Tue, 29 Mar 2016 17:41:59 +0200
Subject: x86/cpufeature: Remove cpu_has_clflush
From: Borislav Petkov <bp@xxxxxxx>
commit 906bf7fda2c9cf5c1762ec607943ed54b6c5b203 upstream.
Use the fast variant in the DRM code.
Signed-off-by: Borislav Petkov <bp@xxxxxxx>
Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
Link: http://lkml.kernel.org/r/1459266123-21878-7-git-send-email-bp@xxxxxxxxx
Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/x86/include/asm/cpufeature.h | 1 -
arch/x86/kernel/cpu/intel.c | 2 +-
arch/x86/kernel/tce_64.c | 2 +-
arch/x86/mm/pageattr.c | 2 +-
drivers/gpu/drm/drm_cache.c | 6 +++---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
6 files changed, 7 insertions(+), 8 deletions(-)
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -378,7 +378,6 @@ extern const char * const x86_bug_flags[
#define cpu_has_aes boot_cpu_has(X86_FEATURE_AES)
#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
-#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH)
#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
#define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -455,7 +455,7 @@ static void init_intel(struct cpuinfo_x8
set_cpu_cap(c, X86_FEATURE_PEBS);
}
- if (c->x86 == 6 && cpu_has_clflush &&
+ if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
(c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
--- a/arch/x86/kernel/tce_64.c
+++ b/arch/x86/kernel/tce_64.c
@@ -40,7 +40,7 @@
static inline void flush_tce(void* tceaddr)
{
/* a single tce can't cross a cache line */
- if (cpu_has_clflush)
+ if (boot_cpu_has(X86_FEATURE_CLFLUSH))
clflush(tceaddr);
else
wbinvd();
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -1481,7 +1481,7 @@ static int change_page_attr_set_clr(unsi
* error case we fall back to cpa_flush_all (which uses
* WBINVD):
*/
- if (!ret && cpu_has_clflush) {
+ if (!ret && boot_cpu_has(X86_FEATURE_CLFLUSH)) {
if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
cpa_flush_array(addr, numpages, cache,
cpa.flags, pages);
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -72,7 +72,7 @@ drm_clflush_pages(struct page *pages[],
{
#if defined(CONFIG_X86)
- if (cpu_has_clflush) {
+ if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
drm_cache_flush_clflush(pages, num_pages);
return;
}
@@ -105,7 +105,7 @@ void
drm_clflush_sg(struct sg_table *st)
{
#if defined(CONFIG_X86)
- if (cpu_has_clflush) {
+ if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
struct sg_page_iter sg_iter;
mb();
@@ -129,7 +129,7 @@ void
drm_clflush_virt_range(void *addr, unsigned long length)
{
#if defined(CONFIG_X86)
- if (cpu_has_clflush) {
+ if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
const int size = boot_cpu_data.x86_clflush_size;
void *end = addr + length;
addr = (void *)(((unsigned long)addr) & -size);
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -466,7 +466,7 @@ i915_gem_execbuffer_relocate_entry(struc
ret = relocate_entry_cpu(obj, reloc, target_offset);
else if (obj->map_and_fenceable)
ret = relocate_entry_gtt(obj, reloc, target_offset);
- else if (cpu_has_clflush)
+ else if (static_cpu_has(X86_FEATURE_CLFLUSH))
ret = relocate_entry_clflush(obj, reloc, target_offset);
else {
WARN_ONCE(1, "Impossible case in relocation handling\n");
Patches currently in stable-queue which might be from bp@xxxxxxx are
queue-4.4/x86-fpu-disable-mpx-when-eagerfpu-is-off.patch
queue-4.4/x86-fpu-disable-avx-when-eagerfpu-is-off.patch
queue-4.4/x86-cpufeature-remove-cpu_has_xmm2.patch
queue-4.4/x86-cpufeature-remove-unused-and-seldomly-used-cpu_has_xx-macros.patch
queue-4.4/x86-cpufeature-replace-cpu_has_avx2-with-boot_cpu_has-usage.patch
queue-4.4/x86-cpufeature-replace-cpu_has_aes-with-boot_cpu_has-usage.patch
queue-4.4/x86-fpu-fix-eager-fpu-handling-on-legacy-fpu-machines.patch
queue-4.4/x86-cpufeature-remove-cpu_has_pse.patch
queue-4.4/x86-cpufeature-remove-cpu_has_osxsave.patch
queue-4.4/x86-mm-pat-x86-cpufeature-remove-cpu_has_pat.patch
queue-4.4/x86-fpu-revert-x86-fpu-disable-avx-when-eagerfpu-is-off.patch
queue-4.4/x86-cpufeature-remove-cpu_has_gbpages.patch
queue-4.4/x86-fpu-fix-early-fpu-command-line-parsing.patch
queue-4.4/x86-cpufeature-remove-cpu_has_x2apic.patch
queue-4.4/x86-cpufeature-remove-cpu_has_clflush.patch
queue-4.4/x86-cpufeature-remove-cpu_has_arch_perfmon.patch
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