On Mon, Jun 11, 2018 at 03:26:54PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.navare@xxxxxxxxx>
>
> For ICL, on Combo PHY the allowed max rates are:
> - HBR3 8.1 eDP (DDIA)
> - HBR2 5.4 DisplayPort (DDIB)
> and for MG PHY/TC DDI Ports allowed DP rates are:
> - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
> - DP on legacy connector - DDIC/D/E/F)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Reviewed-by: James Ausmus <james.ausmus@xxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Signed-off-by: James Ausmus <james.ausmus@xxxxxxxxx>
> [Paulo: bikeshed to keep future platforms on "else".]
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 37b9f62aeb6e..8371159cc192 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -256,6 +256,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
> return 810000;
> }
>
> +static int icl_max_source_rate(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum port port = dig_port->base.port;
> +
> + /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> + * and on Combo PHY Port B the maximum supported is HBR2.
> + */
And what about the other ports? If port B is the only
exception why are we even discussing port A specifically
here?
> + if (port == PORT_B)
> + return 540000;
> +
> + return 810000;
> +}
> +
> static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> @@ -285,10 +299,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> /* This should only be done once */
> WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 10) {
> source_rates = cnl_rates;
> size = ARRAY_SIZE(cnl_rates);
> - max_rate = cnl_max_source_rate(intel_dp);
> + if (INTEL_GEN(dev_priv) == 10)
> + max_rate = cnl_max_source_rate(intel_dp);
> + else
> + max_rate = icl_max_source_rate(intel_dp);
> } else if (IS_GEN9_LP(dev_priv)) {
> source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> --
> 2.14.4
>
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--
Ville Syrjälä
Intel
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