As the swizzling is baked into the tiling pattern, the swizzling has to be consistent across the entire GTT mmap for our tests to work. However, under L-shaped memory configurations on older architectures, the swizzling varied depending on which region the page found itself in -- invalidating our assumptions and ability to predict the tiling pattern. Reported-by: Adric Blake <promarbler14@xxxxxxxxx> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106848 Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> --- tests/gem_mmap_gtt.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tests/gem_mmap_gtt.c b/tests/gem_mmap_gtt.c index 6a332b254..fd60b8ff8 100644 --- a/tests/gem_mmap_gtt.c +++ b/tests/gem_mmap_gtt.c @@ -445,6 +445,24 @@ static int max_tile_width(uint32_t devid, int tiling) return 8 << 10; } +static bool known_swizzling(int fd, uint32_t handle) +{ + struct drm_i915_gem_get_tiling2 { + uint32_t handle; + uint32_t tiling_mode; + uint32_t swizzle_mode; + uint32_t phys_swizzle_mode; + } arg = { + .handle = handle, + }; +#define DRM_IOCTL_I915_GEM_GET_TILING2 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2) + + if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg)) + return false; + + return arg.phys_swizzle_mode == arg.swizzle_mode; +} + static void test_huge_bo(int fd, int huge, int tiling) { @@ -488,6 +506,8 @@ test_huge_bo(int fd, int huge, int tiling) bo = gem_create(fd, PAGE_SIZE); if (tiling) igt_require(__gem_set_tiling(fd, bo, tiling, pitch) == 0); + igt_require(known_swizzling(fd, bo)); + linear_pattern = gem_mmap__gtt(fd, bo, PAGE_SIZE, PROT_READ | PROT_WRITE); for (i = 0; i < PAGE_SIZE; i++) -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
