On Thu, Jun 07, 2018 at 07:13:53PM +0300, Imre Deak wrote:
> While checking workarounds related to the CDCLK PLL, I noticed that the
> DMC firmware bits for WA#1183 are missing for SKL. After that I
> clarified with HW people that it's not needed on SKL, since it doesn't
> support eDP1.4 which would be the only thing requiring the problematic
> CDCLK clock rates. So in theory we shouldn't ever choose these
> frequencies, but add an assert in any case for catching such cases and
> for documentation.
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 704ddb4d3ca7..71045c38e233 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2355,6 +2355,16 @@ static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
> */
> cdclk = skl_calc_cdclk(min_cdclk, vco);
>
> + /*
> + * The following CDCLK rates are unsupported on SKL. In theory this
> + * should never happen since only the eDP1.4 2.16 and 4.32Gbps rates
> + * require it, but eDP1.4 is not supported on SKL, see display
> + * WA#1183.
> + */
> + if (IS_SKYLAKE(to_i915(state->dev)) &&
> + (cdclk == 308571 || cdclk == 617143))
> + DRM_WARN_ONCE("Unsupported CDCLK rate.\n");
Or just WARN(vco == 8640000) in eg. skl_set_cdclk()?
> +
> intel_state->cdclk.logical.vco = vco;
> intel_state->cdclk.logical.cdclk = cdclk;
> intel_state->cdclk.logical.voltage_level =
> --
> 2.13.2
--
Ville Syrjälä
Intel
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