[CC Daniele for his great documentation searching skills.]
On 31/05/2018 19:51, Chris Wilson wrote:
Following the removal of the last workarounds, the only CSB mmio access
is for the old vGPU interface. The mmio registers presented by vGPU do
not require forcewake and can be treated as ordinary volatile memory,
i.e. they behave just like the HWSP access just at a different location.
We can reduce the CSB access inside the irq handler to a set of
read/write/buffer pointers and treat the various paths identically and
not worry about forcewake.
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 12 ---
drivers/gpu/drm/i915/intel_lrc.c | 116 ++++++++++--------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +++--
3 files changed, 65 insertions(+), 86 deletions(-)
[snip]
@@ -1103,16 +1083,11 @@ static void process_csb(struct intel_engine_cs *engine)
} else {
port_set(port, port_pack(rq, count));
}
- }
-
- if (head != execlists->csb_head) {
- execlists->csb_head = head;
- writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
- i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));
- }
+ } while (head != tail);
- if (unlikely(fw))
- intel_uncore_forcewake_put(i915, execlists->fw_domains);
+ writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
+ execlists->csb_read);
This is the write of RING_CONTEXT_STATUS_PTR and the mystery is whether
it is or isn't a shadowed register. We don't have it in the shadowed
list in intel_uncore.c, but we stopped taking forcewake for it after
HWSP conversion and it seems to work regardless. I think if we could
find that it is officially shadowed it would be good to put it in the
list so it is documented properly in code.
Regards,
Tvrtko
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