On Fri, 11 May 2018, Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> wrote: > On Fri, 2018-05-11 at 12:51 -0700, Dhinakaran Pandiyan wrote: >> By moving the check from psr_compute_config() to psr_init_dpcd(), we >> get >> to set the dev_priv->psr.sink_support flag only when the panel is >> capable of changing power state. An additional benefit is that the >> check >> will be performed only at init time instead of every atomic_check. >> >> This should change the psr_basic IGT failures on HSW to skips. >> >> v2: Return early when SET_POWER_CAPABLE bit is 0 (Jose) >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106217 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106346 Pushed to dinq, thanks for the patch and review. BR, Jani. >> Cc: José Roberto de Souza <jose.souza@xxxxxxxxx> >> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> >> Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> >> --- >> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++-- >> drivers/gpu/drm/i915/intel_psr.c | 11 +++++------ >> 2 files changed, 11 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c >> b/drivers/gpu/drm/i915/intel_dp.c >> index dde92e4af5d3..cfd95eaa0d0d 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) >> dev_priv->no_aux_handshake = intel_dp- >> >dpcd[DP_MAX_DOWNSPREAD] & >> DP_NO_AUX_HANDSHAKE_LINK_TRAINING; >> >> - intel_psr_init_dpcd(intel_dp); >> - >> /* >> * Read the eDP display control registers. >> * >> @@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) >> DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) >> sizeof(intel_dp->edp_dpcd), >> intel_dp->edp_dpcd); >> >> + /* >> + * This has to be called after intel_dp->edp_dpcd is filled, >> PSR checks >> + * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] >> + */ >> + intel_psr_init_dpcd(intel_dp); >> + >> /* Read the eDP 1.4+ supported link rates. */ >> if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { >> __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; >> diff --git a/drivers/gpu/drm/i915/intel_psr.c >> b/drivers/gpu/drm/i915/intel_psr.c >> index 8fe6d2f9ab2b..61ade81576f5 100644 >> --- a/drivers/gpu/drm/i915/intel_psr.c >> +++ b/drivers/gpu/drm/i915/intel_psr.c >> @@ -252,9 +252,13 @@ void intel_psr_init_dpcd(struct intel_dp >> *intel_dp) >> >> if (!intel_dp->psr_dpcd[0]) >> return; >> - >> DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", >> intel_dp->psr_dpcd[0]); >> + >> + if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { >> + DRM_DEBUG_KMS("Panel lacks power state control, PSR >> cannot be enabled\n"); >> + return; >> + } >> dev_priv->psr.sink_support = true; >> >> if (INTEL_GEN(dev_priv) >= 9 && >> @@ -642,11 +646,6 @@ void intel_psr_compute_config(struct intel_dp >> *intel_dp, >> return; >> } >> >> - if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { >> - DRM_DEBUG_KMS("PSR condition failed: panel lacks >> power state control\n"); >> - return; >> - } >> - >> crtc_state->has_psr = true; >> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, >> crtc_state); >> DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" >> : ""); > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
